Exploració per tema "FPGA"

Ara es mostren els items 21-40 de 200

    • An FPGA accelerator of the wavefront algorithm for genomics pairwise alignment 

      Haghi, Abbas; Marco-Sola, Santiago; Álvarez Martí, Lluc; Diamantopoulos, Dionysios; Hagleitner, Christoph; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Text en actes de congrés
      Accés obert
      In the last years, advances in next-generation sequencing technologies have enabled the proliferation of genomic applications that guide personalized medicine. These applications have an enormous computational cost due to ...

    • An LMS-based adaptive predistorter for cancelling nonlinear memory effects in RF power amplifiers 

      Montoro López, Gabriel; Gilabert Pinal, Pere Lluís; Bertran Albertí, Eduardo; Cesari Bohigas, Albert; García, José Antonio (2007-12)
      Comunicació de congrés
      Accés obert
      This paper presents the design of an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whoseimplementation and real time adaptation can be fully performed in a Field Programmable Gate Array (FPGA). ...

    • An Optical Burst Switching Control Plane Architecture and its Implementation 

      Triay Marquès, Joan; Rubio, Jesús; Cervelló Pastor, Cristina (2006-09-18)
      Comunicació de congrés
      Accés obert
      This paper proposes a new design and implementation of a control plane for Optical Burst Switched networks. The design is based on the principles of generality, transparency, portability and efficiency. In this way, the ...

    • Analog Signal Adquisition and FFT Application for a Linux Embeded System Lab 

      Montes O'connor, Carlos Jesús (Universitat Politècnica de Catalunya, 2014-05)
      Projecte/Treball Final de Carrera
      Accés obert
      [ANGLÈS] The project goal is to design a platform based on an existing HW/SW embeded Linux system containing a FPGA, within an academic environment. To accomplish that objective, a specific application for signal Adquisition ...

    • Analysis of the communication system of the flight termination system in rockets 

      Arcellares Fernandez De Landa, Galder (Universitat Politècnica de Catalunya, 2023-07-18)
      Treball Final de Grau
      Accés restringit per acord de confidencialitat
      The aim of this thesis is to comprehensively investigate and develop a Flight Termination System (FTS) for ensuring the safety of rockets during their flights. The study focuses on understanding the specific requirements ...

    • Anàlisi de la interconnexió de dispositius lògics programables mitjançant Ethernet 

      Peshevski, Marko (Universitat Politècnica de Catalunya, 2017-02-09)
      Projecte Final de Màster Oficial
      Accés restringit per decisió de l'autor
      En aquest treball s'estudia com fer funcionar Ethernet des d'una placa amb FPGA (de l'anglès Field Programmable Gate Array). Aquests són dispositius electrònics que permeten reprogramar la lògica que contenen dins per ...

    • Análisis de una aplicación de "Pattern Matching" en una FPGA 

      Trueba Calero, Ariadna (Universitat Politècnica de Catalunya, 2008-06-20)
      Projecte/Treball Final de Carrera
      Accés obert

    • Aplicació de la lògica difusa a un algoritme LMS en un entorn FPGA 

      Pertegal Miranda, David (Universitat Politècnica de Catalunya, 2008-11-12)
      Projecte/Treball Final de Carrera
      Accés obert
      Aquest treball fi de carrera presenta el disseny i desenvolupament d’un algoritme de lògica difusa que té per objectiu millorar l’adaptació d’un sistema de linealització basat en tècniques de predistorsió (PD) digital. Aquest ...

    • Automatic transmit power control for power efficient communications in UAS 

      Li, Wantao (Universitat Politècnica de Catalunya, 2020-06-16)
      Projecte Final de Màster Oficial
      Accés obert
      Nowadays, unmanned aerial vehicles (UAV) have become one of the most popular tools that can be used in commercial, scientific, agricultural and military applications. As drones become faster, smaller and cheaper, with the ...

    • AXIOM: a hardware-software platform for cyber physical systems 

      Mazumdar, Somnath; Ayguadé Parra, Eduard; Bettin, Nicola; Bueno Hedo, Javier; Ermini, Sara; Filgueras Izquierdo, Antonio; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier; Montefoschi, Francesco; Oro Garcia, David; Pnevmatikatos, Dionisis; Rizzo, Antonio; Theodoropoulos, Dimitris; Giorgi, Roberto (2016)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Cyber-Physical Systems (CPSs) are widely necessary for many applications that require interactions with the humans and the physical environment. A CPS integrates a set of hardware-software components to distribute, execute ...

    • b8c: an FPGA-friendly sparse matrix representation suitable for the SpMV kernel 

      Oliver, José; Ayguadé Parra, Eduard; Martorell Bofill, Xavier; Álvarez, Carlos (Barcelona Supercomputing Center, 2022-05)
      Text en actes de congrés
      Accés obert
      Sparse Matrix-Vector multiplication (SpMV), computing y = Ax where y and x are dense vectors and A is a sparse matrix, is a key kernel in many HPC applications. SpMV exhibits a kind of memory access that is extremely hard ...

    • Beehive: an FPGA-based multiprocessor architecture 

      Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2009-09-23)
      Projecte Final de Màster Oficial
      Accés obert
      In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for ...

    • Bioinspired onset detection using snava architecture 

      Sekar, Sanjana (Universitat Politècnica de Catalunya, 2014-06-06)
      Projecte/Treball Final de Carrera
      Accés obert
      [ANGLÈS] The main objective of this project is to develop an application which is biologically inspired from one of the functionalities of the human ear and is implemented on a neuromorphic architecture called SNAVA. The ...

    • Bit error rate test for optical communication link using prbs generated by an fpga - hardware implementation 

      Varagur Karthikeyan, Sadhvi (Universitat Politècnica de Catalunya, 2014-06-06)
      Projecte/Treball Final de Carrera
      Accés obert
      Realitzat a/amb:   SASTRA Deemed University
      The Objective involved realizing a PRBS-BERT to analyze the optical link performance. The configuration of the board for the application involved studying the daughter board, the interconnect (i.e. HSMC) and thereby ...

    • Bit error rate test for optical communication link using prbs generated by an fpga - system design 

      Vairavel, Sindhu (Universitat Politècnica de Catalunya, 2014-06-06)
      Projecte/Treball Final de Carrera
      Accés obert
      Bit Error Rate Testing(BERT) was implemented using Cyclone III FPGA Starter Kit along with THDB_ADA board and interfaced with several kilometers long optical fiber, to study the link performance of the optical communication ...

    • Cabecera Radio Remota utilizando LimeSDR y ODROID - XU4 

      Cerezo Tobias, Jordi (Universitat Politècnica de Catalunya, 2018-02-02)
      Treball Final de Grau
      Accés obert
      The Software Defined Radio (SDR), unlike conventional radio systems implemented only by hardware, has had a great impact thanks to the great flexibility offered by the software. The objective of this work has been to develop ...

    • Calibration of a TDL-TDC with ML methods 

      Costa Cañones, Daniel (Universitat Politècnica de Catalunya, 2022-06-09)
      Projecte Final de Màster Oficial
      Accés restringit per acord de confidencialitat
      Realitzat a/amb:   Politecnico di Milano

    • Characterization and optimization of a multi-channel, FPGA-based Time-to-Digital Converter 

      Compte Prades, Joel (Universitat Politècnica de Catalunya, 2023-09-06)
      Projecte Final de Màster Oficial
      Accés obert
      Realitzat a/amb:   Institut de Ciències Fotòniques (ICFO)
      High-resolution time measurement is a fundamental building block on a wide variety of applications such as time-of-flight based systems, single-photon microscopy and quantum communications. FPGA-based TDCs are the preferred ...

    • Characterization of a coherent hardware accelerator framework for SoCs 

      López Paradís, Guillem; Venu, Balaji; Armejach Sanosa, Adrià; Moretó Planas, Miquel (Springer, 2023)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Accelerators rich architectures have become the standard in today’s SoCs. After Moore’s law diminish, it is common to only dedicate a fraction of the area of the SoC to traditional cores and leave the rest of space for ...

    • Co-diseño hardware-software de una unidad en coma flotante para microprocesador de 32 bits 

      Lumbiarres López, Rubén (Universitat Politècnica de Catalunya, 2008-06)
      Projecte/Treball Final de Carrera
      Accés obert
      El uso de números en coma flotante es muy habitual en la programación software para la resolución de todo tipo de algoritmos. Dada la particular forma de codificar valores en este formato, definida en la norma IEEE 754, ...