Ara es mostren els items 21-40 de 45

  • Light NUCA: a proposal for bridging the inter-cache latency gap 

    Suárez, Dario; Monreal Arnal, Teresa; Vallejo, Fernando; Beivide Palacio, Julio Ramón; Viñals Yufera, Víctor (IEEE Computer Society, 2009)
    Comunicació de congrés
    Accés obert
    To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). ...
  • LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors 

    Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María (2009-05-14)
    Report de recerca
    Accés obert
    The increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. Non Uniform Cache Architectures (NUCA) has been introduced to deal ...
  • Massive query expansion by exploiting graph knowledge bases for image retrieval 

    Guisado Gámez, Joan; Domínguez Sal, David; Larriba Pey, Josep (Association for Computing Machinery (ACM), 2014)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Annotation-based techniques for image retrieval suffer from sparse and short image textual descriptions. Moreover, users are often not able to describe their needs with the most appropriate keywords. This situation is a ...
  • Memorias SRAM en "Hardware Description Language (HDL)" para una plataforma de simulación de codigos en HDL. 

    Bartra Carreras, Oscar (Universitat Politècnica de Catalunya, 2010-04-16)
    Treball Final de Grau
    Accés obert
  • Memòries 

    Amat Girbau, Josep; Ferrer, F. (Asociación de Técnicos de Informática, 1980)
    Article
    Accés obert
  • Memòries externes 

    Puigjaner Trepat, Ramón (Asociación de Técnicos de Informática, 1980)
    Article
    Accés obert
  • Memory Dependence Prediction Methods Study and Improvement Proposals 

    Pflücker López, Otto Fernando (Universitat Politècnica de Catalunya, 2011-03-28)
    Projecte Final de Màster Oficial
    Accés obert
    English: Nowadays, most modern high performance processors employ out-of-order (O3) execution. In these processors, instructions are executed as soon as possible increasing in this way the instruction level parallelism ...
  • Memristive crossbar memory lifetime evaluation and reconfiguration strategies 

    Pouman, Peyman; Amat, Esteve; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016-06-20)
    Article
    Accés obert
    Among the emerging technologies and devices for highly scalable and low power memory architectures, memristors are considered as one of the most favorable alternatives for next generation memory technologies. They are ...
  • On the usefulness of object tracking techniques in performance analysis 

    Llort Sánchez, Germán; Servat, Harald; González García, Juan; Giménez Lucas, Judit; Labarta Mancho, Jesús José (Association for Computing Machinery (ACM), 2013)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Understanding the behavior of a parallel application is crucial if we are to tune it to achieve its maximum performance. Yet the behavior the application exhibits may change over time and depend on the actual execution ...
  • Optimization of the SD2 memory system 

    Pacheco Fuentes, Adrià; Alvarez Iglesias, Ricard (Universitat Politècnica de Catalunya, 2012-07-11)
    Treball Final de Grau
    Accés obert
    As far as is evidenced, man has sought the answers to his deepest questions by observing the sky. The findings and studies that have been made in this way have helped us know the planet where we live and our situation in ...
  • Performance impact of a slower main memory: a case study of STT-MRAM in HPC 

    Asifuzzaman, Kazi; Pavlovic, Milan; Radulovic, Milan; Zaragoza, David; Kwon, Ohseong; Ryoo, Kyung-Chang; Radojkovic, Petar (Barcelona Supercomputing Center, 2017-05-04)
    Text en actes de congrés
    Accés obert
    Memory systems are major contributors to the deployment and operational costs of large-scale HPC clusters [1][2][3], as well as one of the most important design parameters that significantly affect system performance. In ...
  • Performance impacts with reliable parallel file systems at exascale level 

    Nou Castell, Ramon; Miranda, Alberto; Cortés, Toni (Springer, 2015)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The introduction of Exascale storage into production systems will lead to an increase on the number of storage servers needed by parallel file systems. In this scenario, parallel file system designers should move from the ...
  • Plataforma per a anàlisi de performance en navegació d'alt nivell 

    Sagre Martinez, Xavier (Universitat Politècnica de Catalunya, 2011-06-22)
    Projecte/Treball Final de Carrera
    Accés obert
    Català: El projecte proposa l anàlisi, disseny i implementació d una nova aplicació amb un conjunt de funcionalitats (mecanismes) orientades a l emmagatzematge i tractament de les dades recol lectades pels sensors dels ...
  • PMSS: a programmable memory system and scheduler for complex memory patterns 

    Hussain, Tassadaq; Haider, Amna; Ayguadé Parra, Eduard (2014-10)
    Article
    Accés restringit per política de l'editorial
    HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. ...
  • Processing data where it makes sense in modern computing systems: enabling in-memory computation 

    Mutlu, Onur (Barcelona Supercomputing Center, 2019)
    Altres
    Accés obert
  • RADIO: managing the performance of large, distributed storage systems 

    Facultat d'Informàtica de Barcelona; Brandt, Scott A. (2009-07-07)
    Audiovisual
    Accés obert
    Els sistemes informàtics d’altes prestacions continuen creixent en grandària i complexitat, i sovint han de gestionar moltes tasques diferents simultàniament. El subsistema d’entrada i sortida és freqüentment un coll ...
  • Reducing fetch architecture complexity using procedure inlining 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    Fetch engine performance is seriously limited by the branch prediction table access latency. This fact has lead to the development of hardware mechanisms, like prediction overriding, aimed to tolerate this latency. However, ...
  • Reliability issues in RRAM ternary memories affected by variability and aging mechanisms 

    Rubio Sola, Jose Antonio; Escudero, Manuel; Pouyan, Peyman (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and ...
  • Sesquickselect: One and a half pivots for cache-efficient selection 

    Martínez Parra, Conrado; Nebel, Markus; Wild, Sebastian (Curran, 2019)
    Text en actes de congrés
    Accés obert
    Because of unmatched improvements in CPU performance, memory transfers have become a bottleneck of program execution. As discovered in recent years, this also affects sorting in internal memory. Since partitioning around ...
  • Systematic and random variability analysis of two different 6T-SRAM layout topologies 

    Amat Bertran, Esteve; Amatlle, E.; Gómez González, Sergio; Aymerich Capdevila, Nivard; García Almudéver, Carmen; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013-09)
    Article
    Accés obert