Exploració per tema "Asynchronous circuits"
Ara es mostren els items 21-40 de 64
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Designing asynchronous circuits from behavioural specifications with internal conflicts
(Institute of Electrical and Electronics Engineers (IEEE), 1994)
Text en actes de congrés
Accés obertThe paper presents a systematic method for synthesizing asynchronous circuits from event-based specifications with conflicts on output signals. It describes a set of semantic-preserving transformations performed at the ... -
Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
(2006-10)
Article
Accés obertAsynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design ... -
Efficient encoding schemes for symbolic analysis of Petri nets
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertPetri nets are a graph-based formalism appropriate to model concurrent systems such as asynchronous circuits or network protocols. Symbolic techniques based on Binary Decision Diagrams (BDDs) have emerged as one of the ... -
Elastic circuits
(2009-10)
Article
Accés obertElasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with ... -
Elasticity and Petri nets
(2008-01)
Article
Accés obertDigital electronic systems typically use synchronous clocks and primarily assume fixed duration of their operations to simplify the design process. Time elastic systems can be constructed either by replacing the clock with ... -
Encoding large asynchronous controllers with ILP techniques
(2008-01)
Article
Accés obertState encoding is one of the most difficult problems in the synthesis of asynchronous controllers. This paper presents a method that can solve the problem of large controllers specified with signal transition graphs. The ... -
Flujo de diseño asíncrono con la biblioteca DCVSL_LIB para ES2 ECPD10
(Omron, 1996)
Text en actes de congrés
Accés obertEn el presente trabajo se pretende abordar la metodología a seguir durante el flujo de diseño de un circuito asíncrono orientado a prestaciones, utilizando la biblioteca DCVSL_LIB para aplicaciones asíncronas que hemos ... -
Formal verification of safety properties in timed circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertThe incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative ... -
From synchronous to asynchronous: an automatic approach
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertThis paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case study shows the applicability of the method ... -
Handshake protocols for de-synchronization
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertDe-synchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for de-synchronization and formally proves their correctness. ... -
Hardware and Petri nets: application to asynchronous circuit design
(Springer, 2000-06)
Article
Accés obertAsynchronous circuits is a discipline in which the theory of concurrency is applied to hardware design. This paper presents an overview of a design framework in which Petri nets are used as the main behavioral model for ... -
Hierarchical gate-level verification of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertThis paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on ... -
High-level synthesis of asynchronous systems: Scheduling and process synchronization
(Institute of Electrical and Electronics Engineers (IEEE), 1993)
Text en actes de congrés
Accés obertBasic concepts for scheduling algorithms and control synthesis in high-level synthesis of asynchronous circuits are defined. Two scheduling strategies are presented and evaluated. Experiments on different benchmarks show ... -
Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertState coding conflict detection is a fundamental part of synthesis of asynchronous concurrent systems from their specifications as signal transition graphs (STGs), which are a special kind of labelled Petri nets. The paper ... -
Lazy transition systems and asynchronous circuits synthesis with relative timing assumptions
(2002-02)
Article
Accés obertThis paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness ... -
Lazy transition systems: application to timing optimization of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertThe paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the ... -
Logic decomposition of speed-independent circuits
(1999-02)
Article
Accés obertLogic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional ... -
Logic design of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertSummary form only given. This tutorial aims at motivating the audience to consider asynchronous circuits as a competitive alternative to solve some of the design problems inherent to submicron technologies. One of the main ... -
Methodology and tools for state encoding in asynchronous circuit synthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertThis paper proposes a state encoding method for asynchronous circuits based on the theory of regions. A region in a Transition System is a set of states that “behave uniformly” with respect to a given transition (value ... -
Motores sin escobillas:accionamientos sincronos autopilotados, excitados con imanes permanentes
(1991-12-01)
Article
Accés restringit per política de l'editorialLos accionamientos síncronos autopilotados excitados con imanes permanentes están ocupando posiciones relevantes en el mercado de los accionamientos eléctricos. En el presente artículo, tras una descripción morfológica de ...
