Ara es mostren els items 21-40 de 42

    • Lazy transition systems and asynchronous circuits synthesis with relative timing assumptions 

      Cortadella, Jordi; Kishinevsky, Michael; Burns, Steven M.; Kondratyev, Alex; Lavagno, Luciano; Stevens, Kenneth S.; Taubin, Alexander; Yakovlev, Alex (2002-02)
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      This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness ...
    • Lazy transition systems: application to timing optimization of asynchronous circuits 

      Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Taubin, Alexander; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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      The paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the ...
    • Logic decomposition of speed-independent circuits 

      Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Lavagno, Luciano; Yakovlev, Alex (1999-02)
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      Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional ...
    • Metastability in better-than-worst-case designs 

      Beer, Salomon; Cannizzaro, Marco; Cortadella, Jordi; Ginosar, Ran; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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      Better-Than-Worst-Case-Designs use timing speculation to run with a cycle period faster than the one required for worst-case conditions. This speculation may produce timing violations and metastability that result in ...
    • Methodology and tools for state encoding in asynchronous circuit synthesis 

      Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1996)
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      This paper proposes a state encoding method for asynchronous circuits based on the theory of regions. A region in a Transition System is a set of states that “behave uniformly” with respect to a given transition (value ...
    • Mix & Latch: An optimization flow for high-performance designs with single-clock mixed-polarity latches and flip-flops 

      Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 2023-04-10)
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      Flip-flops are the most used sequential elements in synchronous circuits, but designs based on latches can operate at higher frequencies and occupy less area. Techniques to increase the maximum operating frequency of ...
    • Narrowing the margins with elastic clocks 

      Cortadella, Jordi; Lavagno, Luciano; Amiri, Djavad; Casanova Bachs, Jonàs; Macián, Carlos; Martorell, Ferran; Moya, Juan A.; Necchi, Luca; Sokolov, Danil; Tuncer, Emre (Institute of Electrical and Electronics Engineers (IEEE), 2010)
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      The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate ...
    • Partial order based approach to synthesis of speed-independent circuits 

      Semenov, Alex; Yakovlev, Alex; Pastor Llorens, Enric; Peña Basurto, Marco Antonio; Cortadella, Jordi; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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      This paper introduces a novel technique for synthesis of speed-independent circuits from their Signal Transition Graph specifications. The new method uses partial order in the form of the STG-unfolding segment to derive ...
    • Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers 

      Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (1997-03)
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      Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it ...
    • Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers 

      Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (Universitat Politècnica de Catalunya (UPC), 1996)
      Text en actes de congrés
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      Petrifyis a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition ...
    • Power-optimal mapping of CNN applications to cloud-based Multi-FPGA platforms 

      Shan, Junnan; Lazarescu, Mihai T.; Cortadella, Jordi; Lavagno, Luciano; Casu, Mario R. (2020-12)
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      Multi-FPGA platforms like Amazon Web Services F1 are perfect to accelerate multi-kernel pipelined applications, like Convolutional Neural Networks (CNNs). To reduce energy consumption, we propose to upload at runtime the ...
    • Quasi-static scheduling for concurrent architectures 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Watanabe, Yosinori (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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      We present a synthesis approach for reactive systems that aims at minimizing the overhead introduced by the operating system and the interaction among the concurrent tasks, while considering multiple concurrent execution ...
    • Quasi-static scheduling of independent tasks for reactive systems 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Passerone, Claudio; Watanabe, Yosinori (Springer, 2002-06)
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      Accés obert
      The synthesis of a reactive system generates a set of concurrent tasks coordinated by an operating system. This paper presents a synthesis approach for reactive systems that aims at minimizing the overhead introduced by ...
    • Quasi-static scheduling of independent tasks for reactive systems 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Passerone, Claudio; Watanabe, Yosinori (2005-10)
      Article
      Accés obert
      A reactive system must process inputs from the environment at the speed and with the delay dictated by the environment. The synthesis of reactive software from a modular concurrent specification model generates a set of ...
    • Reactive clocks with variability-tracking jitter 

      Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits ...
    • SafeRazor: Metastability-robust adaptive clocking in resilient circuits 

      Cannizzaro, Marco; Beer, Salomon; Cortadella, Jordi; Ginosar, Ran; Lavagno, Luciano (2015-09-01)
      Article
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      Razor-based circuits can run faster or at a lower voltage than those designed to work at the worst case corner. However, all known implementations are prone to failures due to the non-deterministic timing behavior introduced ...
    • Synthesizing Petri nets from state-based models 

      Cortadella, Jordi; Kishinevsky, Michael; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1995)
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      This paper presents a method to synthesize labeled Petri nets from state-based models. Although state-based models (such as finite state machines) are a powerful formalism to describe the behavior of sequential systems, ...
    • Task generation and compile-time scheduling for mixed data-control embedded software 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Massot, Marc; Moral Boadas, Sandra; Passerone, Claudio; Watanabe, Yosinori; Sangiovanni-Vincentelli, Alberto (1999-11)
      Report de recerca
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      A method for synthesizing code for the software component of a system is proposed. The specification is given as a set of concurrent processes that communicate through channels. Each process is a sequential program that ...
    • Task generation and compile-time scheduling for mixed data-control embedded software 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Massot, Marc; Moral Boadas, Sandra; Passerone, Claudio; Watanabe, Yosinori; Sangiovanni-Vincentelli, Alberto (Association for Computing Machinery (ACM), 2000)
      Text en actes de congrés
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      The problem of optimal software synthesis for concurrent processes to be implemented on a single processor is addressed. The approach calls for the representation of the concurrent processes with Petri nets that give a ...
    • Technology mapping for speed-independent circuits: Decomposition and resynthesis 

      Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1997)
      Text en actes de congrés
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      This paper presents theory and practical implementation of a method for multi-level logic synthesis of speed-independent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but ...