Browsing by Author "Kondratyev, Alex"
Now showing items 21-32 of 32
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Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
(1997-03)
Article
Open AccessPetrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it ... -
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
(Universitat Politècnica de Catalunya (UPC), 1996)
Conference report
Open AccessPetrifyis a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition ... -
Quasi-static scheduling for concurrent architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Conference report
Open AccessWe present a synthesis approach for reactive systems that aims at minimizing the overhead introduced by the operating system and the interaction among the concurrent tasks, while considering multiple concurrent execution ... -
Quasi-static scheduling of independent tasks for reactive systems
(Springer, 2002-06)
Article
Open AccessThe synthesis of a reactive system generates a set of concurrent tasks coordinated by an operating system. This paper presents a synthesis approach for reactive systems that aims at minimizing the overhead introduced by ... -
Quasi-static scheduling of independent tasks for reactive systems
(2005-10)
Article
Open AccessA reactive system must process inputs from the environment at the speed and with the delay dictated by the environment. The synthesis of reactive software from a modular concurrent specification model generates a set of ... -
Structural methods for the synthesis of speed-independent circuits
(1998-11)
Article
Open AccessAsynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal transitions. The synthesis of concurrent systems implies the analysis of a vast state space that often requires computationally ... -
Structural methods for the synthesis of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Conference report
Open AccessMost existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based ... -
Task generation and compile-time scheduling for mixed data-control embedded software
(Association for Computing Machinery (ACM), 2000)
Conference report
Open AccessThe problem of optimal software synthesis for concurrent processes to be implemented on a single processor is addressed. The approach calls for the representation of the concurrent processes with Petri nets that give a ... -
Task generation and compile-time scheduling for mixed data-control embedded software
(1999-11)
Research report
Open AccessA method for synthesizing code for the software component of a system is proposed. The specification is given as a set of concurrent processes that communicate through channels. Each process is a sequential program that ... -
Technology mapping for speed-independent circuits: Decomposition and resynthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessThis paper presents theory and practical implementation of a method for multi-level logic synthesis of speed-independent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but ... -
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessThis paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, ... -
What is the cost of delay insensitivity?
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessDeep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour ...
