Browsing by Author "Kishinevsky, Michael"
Now showing items 21-36 of 36
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Lazy transition systems and asynchronous circuits synthesis with relative timing assumptions
(2002-02)
Article
Open AccessThis paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness ... -
Lazy transition systems: application to timing optimization of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessThe paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the ... -
Logic decomposition of speed-independent circuits
(1999-02)
Article
Open AccessLogic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional ... -
Methodology and tools for state encoding in asynchronous circuit synthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Conference report
Open AccessThis paper proposes a state encoding method for asynchronous circuits based on the theory of regions. A region in a Transition System is a set of states that “behave uniformly” with respect to a given transition (value ... -
New region-based algorithms for deriving bounded Petri nets
(Institute of Electrical and Electronics Engineers (IEEE), 2010-03)
Article
Open AccessThe theory of regions was introduced in the early nineties as a method to bridge state and event-based models. This paper tackles the problem of deriving a Petri net from a state-based model, using the theory of regions. ... -
On the performance evaluation of multi-guarded marked graphs with single-server semantics
(2010-09)
Article
Open AccessIn discrete event systems, a given task can start executing when all the required input data are available. The required input data for a given task may change along the evolution of the system. A way of modeling this ... -
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
(1997-03)
Article
Open AccessPetrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it ... -
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
(Universitat Politècnica de Catalunya (UPC), 1996)
Conference report
Open AccessPetrifyis a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition ... -
Physical-aware link allocation and route assignment for chip multiprocessing
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Conference report
Open AccessThe architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining ... -
Symbolic performance analysis of elastic systems
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Conference report
Open AccessElastic systems, either synchronous or asynchronous, can be optimized for the average-case performance when they have units with early evaluation or variable latency. The performance evaluation of such systems using ... -
Synchronous elastic networks
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Conference report
Open AccessWe formally define - at the stream transformer level - a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove ... -
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessThis paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions ... -
Synthesis of synchronous elastic architectures
(Association for Computing Machinery (ACM), 2006)
Conference report
Open AccessA simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automatable design methodology. With this approach, ... -
Synthesizing Petri nets from state-based models
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Conference report
Open AccessThis paper presents a method to synthesize labeled Petri nets from state-based models. Although state-based models (such as finite state machines) are a powerful formalism to describe the behavior of sequential systems, ... -
Technology mapping for speed-independent circuits: Decomposition and resynthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessThis paper presents theory and practical implementation of a method for multi-level logic synthesis of speed-independent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but ... -
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessThis paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, ...
