Ara es mostren els items 21-22 de 22

    • Software-controlled priority characterization of POWER5 processor 

      Boneti, Carlos; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Cher, Chen-Yong; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Text en actes de congrés
      Accés obert
      Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded ...
    • The MPsim simulation tool 

      Acosta Ojeda, Carmelo Alexis; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009)
      Report de recerca
      Accés obert
      In order to evaluate novel ideas, computer architects require simulation tools which model a target architecture. According to the specific accuracy requirements we find very specific simulators, which model a single ...