Exploració per altres contribucions "Moll Echeto, Francisco de Borja"
Ara es mostren els items 21-40 de 50
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Design of an Output Interface for an In-Memory-Computing CNN Accelerator
(Universitat Politècnica de Catalunya, 2020-11-27)
Projecte Final de Màster Oficial
Accés obertAnalog in-memory computing accelerators are one of the most promising solutions to reduce data movement limitations in deep neural networks (DNNs). While analog in-memory computing accelerators have been studied in many ... -
Design of variability compensation architectures of digital circuits with adaptive body bias
(Universitat Politècnica de Catalunya, 2016-05-24)
Projecte Final de Màster Oficial
Accés obertThe most critical concern in circuit is to achieve high level of performance with very tight power constraint. As the high performance circuits moved beyond 45nm technology one of the major issues is the parameter variation ... -
Design optimization of a CMOS-MEMS resonator for molecular adherence applications
(Universitat Politècnica de Catalunya, 2016-06)
Projecte Final de Màster Oficial
Accés restringit per decisió de l'autor
Realitzat a/amb: Universitat de les Illes BalearsIntensive research within the biomedical domain during the last decade has raised an increasing interest on the capabilities of disease diagnosis based on exhaled breath analysis. While human exhaled breath has been shown ... -
Design, implementation and evaluation of post-quantum cryptography accelerators in 22nm FDSOI technology
(Universitat Politècnica de Catalunya, 2023-02-02)
Projecte Final de Màster Oficial
Accés restringit per acord de confidencialitatThis thesis aims to design and implement a Post-Quantum Cryptographic (PQC) algorithm accelerator to integrate it inside a System On Chip (SoC) for FPGA and ASIC targets. The accelerated PQC algorithm is called CRYSTALS-Kyber, ... -
Disseny d'un microgenerador amb làmines piezoelèctriques
(Universitat Politècnica de Catalunya, 2010)
Projecte/Treball Final de Carrera
Accés obert -
Efficient implementation of a Content-Addressable Memory in a 22nm technology
(Universitat Politècnica de Catalunya, 2023-06)
Projecte Final de Màster Oficial
Accés obertMemory design is a key aspect of a digital processing system. Usually, memories take a considerable amount of space which on a design size limited ASIC, it can be a problem fitting every desired functionality. Typically, ... -
Eina d'extracció i ajust automàtic per a models específics de paràmetres de circuits microelectrònics
(Universitat Politècnica de Catalunya, 2016)
Projecte/Treball Final de Carrera
Accés obert
Realitzat a/amb: Universitat de les Illes BalearsThis project presents the development of a software tool that automates the model extraction process at standard cell level, from the cells electrical level simulations. Starting from the standard cells library files, ... -
Evaluación de las variaciones de proceso litográficas en circuitos integrados
(Universitat Politècnica de Catalunya, 2010)
Projecte/Treball Final de Carrera
Accés obertEl objetivo del proyecto es evaluar las variaciones de procedo sistemáticas en las longitudes de canal del transistor. Estas variaciones afectan a la respuesta esperada del circuito modificando la energía consumida y sus ... -
Evaluation of open-source synthesis tools for ASIC Design
(Universitat Politècnica de Catalunya, 2023-10-20)
Treball Final de Grau
Accés obert
Realitzat a/amb: Barcelona Supercomputing CenterEl paper indispensable de les eines d'Automatització del Disseny Electrònic (EDA) en el disseny de Circuits Integrats d'Aplicació Específica (ASICs) és irrefutable. El monumental progrés tecnològic presenciat en les últimes ... -
Exploration of FDSOI back-biasing techniques to hinder cryptographic attacks based on leakage current
(Universitat Politècnica de Catalunya, 2023-10-18)
Tesi
Accés obert(English) Cryptography is the science that studies how to achieve secure communication between multiple parties. Under the assumption that any message transmitted is to be ultimately intercepted, the endeavors of cryptography ... -
From FPGA to ASIC: A RISC-V processor experience
(Universitat Politècnica de Catalunya, 2019-10-25)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Instituto Politécnico Nacional. Centro de Investigación en ComputaciónThis work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC. -
Functional and formal verification on submodules of a vector processing unit based on RISC-V V-extension
(Universitat Politècnica de Catalunya, 2020-09)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Politecnico di TorinoThis thesis was developed while working at Barcelona Supercomputing Center, a research center specialized in High Performance Computing and investigation in many fields, such as cloud computing, bioinformatics, material ... -
Human body activity energy harvesting system with a piezoelectric transducer
(Universitat Politècnica de Catalunya, 2017-06)
Treball Final de Grau
Accés obertThe objective of this project is the energy quantification that can be collected from the movement of the human body with a simple scheme of conversion with a piezoelectric transducer. It will be examined how to accumulate ... -
Impact of physical low power techniques in a RISC-V processor
(Universitat Politècnica de Catalunya, 2021-01-28)
Projecte Final de Màster Oficial
Accés obertPower consumption is one of the main aspects in the overall performance of en electronic circuit. Design for low power can be applied from algorithm through the physical implementation of the integrated circuit. In this ... -
Impact of using approximate FP multipliers in a neural network
(Universitat Politècnica de Catalunya, 2022-05-25)
Treball Final de Grau
Accés obertEn els últims anys, computació aproximada ha estat un dels temes més populars en camps com el reconeixement d'imatges, l'anàlisi d'imatges, el processament del llenguatge. Molts científics han estat estudiant com aprofitar ... -
Implementation feasibility of an integrated LPDDR4 PHY block
(Universitat Politècnica de Catalunya, 2022-06)
Projecte Final de Màster Oficial
Accés obertOne of the bottlenecks in the performance of academic RISC-V ASIC processors is high-speed memory access. The use of high speed DDR RAM chips on the board requires the integration in the ASIC of a very complex physical ... -
Implementation of a deep learning accelerator in an open-source PDK
(Universitat Politècnica de Catalunya, 2023-09-12)
Projecte Final de Màster Oficial
Accés obertThis master's thesis delves into the realm of open-source ASIC design, unveiling the vast potential of utilizing open-source tools in the development process. In recent times, a myriad of EDA tools and PDK have appeared, ... -
In-memory-computing CNN accelerator employing charge-domain compute
(Universitat Politècnica de Catalunya, 2020-11)
Projecte Final de Màster Oficial
Accés obertHigh-dimensional matrix-vector-multiplications (MVM) are the main operations of deep neural networks (DNN). As the size of DNNs increases, data movement becomes a problem and limits their performance. Analog in-memory ... -
Layout regularity for design and manufacturability
(Universitat Politècnica de Catalunya, 2012-10-02)
Tesi
Accés obertIn nowadays nanometer technology nodes, the semiconductor industry has to deal with the new challenges associated to technology scaling. On one hand, process developers face increasing manufacturing cost and variability, ... -
Monitor amb control strategies to reduce the impact of process variations in digital circuits
(Universitat Politècnica de Catalunya, 2015-12-14)
Tesi
Accés obertAs CMOS technology scales down, Process, Voltage, Temperature and Ageing (PVTA) variations have an increasing impact on the performance and power consumption of electronic devices. These issues may hold back the continuous ...
