Now showing items 21-40 of 66

  • Error probability in synchronous digital circuits due to power supply noise 

    Martorell Cid, Ferran; Pons, M; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja (???, 2007)
    Conference report
    Open Access
    This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered ...
  • Examen Final 

    Moreno Aróstegui, Juan Manuel; Cabestany Moncusí, Joan; Rubio, Antonio; Moll Echeto, Francisco de Borja (Universitat Politècnica de Catalunya, 2014-01-10)
    Exam
    Restricted access to the UPC academic community
  • Examen Final 

    Aragonès Cervera, Xavier; Moll Echeto, Francisco de Borja; Rubio, Antonio; Altet Sanahujes, Josep; Gómez, Sergio (Universitat Politècnica de Catalunya, 2013-06-26)
    Exam
    Restricted access to the UPC academic community
  • Experience on material implication computing with an electromechanical memristor emulator 

    Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Escudero López, Manuel; Zuin, Stefano; Vourkas, Ioannis; Sirakoulis, Georgios (IEEE Press, 2016)
    Conference report
    Open Access
    Memristors are being considered as a promising emerging device able to introduce new paradigms in both data storage and computing. In this paper the authors introduce the concept of a quasi-ideal experimental device that ...
  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 

    González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
    Conference lecture
    Restricted access - publisher's policy
    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ...
  • FOCSI: A new layout regularity metric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
    External research report
    Open Access
    Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...
  • Influència de les Interconnexions en Disseny Microelectrònic 

    Moll Echeto, Francisco de Borja (Universitat Politècnica de Catalunya, 1995-03-31)
    Doctoral thesis
    Open Access
    Debido a los actuales niveles de integración que permite la tecnología de fabricación de circuitos integrados, las interconexiones juegan cada vez un papel más importante en el comportamiento de dichos circuitos introduciendo ...
  • Insights into tunnel FET-based charge pumps and rectifiers for energy harvesting applications 

    Nunes Cavalheiro, David Manuel; Moll Echeto, Francisco de Borja; Valtchev, Stanimir (2017-03-01)
    Article
    Open Access
    In this paper, the electrical characteristics of tunnel field-effect transistor (TFET) devices are explored for energy harvesting front-end circuits with ultralow power consumption. Compared with conventional thermionic ...
  • Lithography aware regular cell design based on a predictive technology model 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2010-12)
    Article
    Restricted access - publisher's policy
    As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ...
  • Lithography aware regular cell design based on a predictive technology model 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2010)
    Conference report
    Open Access
    As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ...
  • Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Mauricio Ferré, Juan (2014-07-01)
    Article
    Open Access
    A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables ...
  • Local variations compensation with DLL-based body bias generator for UTBB FD-SOI technology 

    Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Restricted access - publisher's policy
    Local variations are increasingly important in new technologies. This paper presents the design of adaptive circuits based on the concept of Adaptive Body Bias Islands and a Forward and Reverse Body Bias Generator for FDSOI ...
  • Logic synthesis for manufacturability considering regularity and lithography printability 

    Machado, Lucas; Dal Bem, Vinicius; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio; Ribas, Renato P.; Reis, André Inacio (IEEE Computer Society Publications, 2013)
    Conference report
    Restricted access - publisher's policy
    This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, ...
  • Measurements of process variability in 40-nm regular and nonregular layouts 

    Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio (2014-02-01)
    Article
    Restricted access - publisher's policy
    As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts ...
  • Measuring the tolerance of self-adaptive clocks to supply voltage noise 

    Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Cortadella, Jordi (2011)
    Conference report
    Open Access
    Simultaneous switching noise has become an important issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. ...
  • Memristive logic in crossbar memory arrays: Variability-aware design for higher reliability 

    Escudero López, Manuel; Vourkas, Ioannis; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja (2019-01-01)
    Article
    Open Access
    The advent of the first TiO 2 -based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and ...
  • Monitor strategies for variability reduction considering correlation between power and timing variability 

    Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja; Altet Sanahujes, Josep (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Conference report
    Restricted access - publisher's policy
    As CMOS technology scales, Process, Voltage and Temperature (PVT) variations have an increasing impact on, performance and power consumption of the electronic devices. Variability causes an undesirable dispersion of ...
  • New redundant logic design concept for high noise and low voltage scenarios 

    García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2011-12)
    Article
    Restricted access - publisher's policy
    This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ...
  • Noise generation and coupling mechanisms in deep-submicron IC's 

    Aragonès Cervera, Xavier; González Jiménez, José Luis; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2002-09)
    Article
    Open Access
    On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques ...
  • Novel charge pump converter with Tunnel FET devices for ultra-low power energy harvesting sources 

    Nunes Cavalheiro, David Manuel; Moll Echeto, Francisco de Borja; Valtchev, Stanimir (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference lecture
    Open Access
    Compared to conventional technologies, the superior electrical characteristics of III-V Tunnel FET (TFET) devices can highly improve the process of energy harvesting conversion at ultra-low input voltage operation ...