Now showing items 21-40 of 93

  • Clock gate on abort: Towards energy-efficient hardware transactional memory 

    Sanyal, Sutirtha; Roy, Sourav; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2009)
    Conference report
    Open Access
    Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a ...
  • Commit on overflow 

    Stipic, Srdjan; Armejach, Adrià; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2014)
    External research report
    Open Access
    Current commercial CPUs have hardware support for speculative lock elision (SLE). SLE tries to elide the lock by speculatively executing lock protected critical section. If the speculation fails, SLE acquires the lock and ...
  • CRC-based memory reliability for task-parallel HPC applications 

    Subasi, Omer; Unsal, Osman Sabri; Labarta Mancho, Jesús José; Yalcin, Gulay; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    Memory reliability will be one of the major concerns for future HPC and Exascale systems. This concern is mostly attributed to the expected massive increase in memory capacity and the number of memory devices in Exascale ...
  • DaSH: a benchmark suite for hybrid dataflow and shared memory programming models 

    Gajinov, Vladimir; Stipic, Srdjan; Eric, Igor; Unsal, Osman Sabri; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (2015-06-01)
    Article
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    The current trend in development of parallel programming models is to combine different well established models into a single programming, model in order to support efficient implementation of a wide range of real world ...
  • DaSH: a benchmark suite for hybrid dataflow and shared memory programming models: with comparative evaluation of three hybrid dataflow models 

    Gajinov, Vladimir; Stipic, Srdjan; Eric, Igor; Unsal, Osman Sabri; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (Association for Computing Machinery (ACM), 2014)
    Conference report
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    The current trend in development of parallel programming models is to combine different well established models into a single programming model in order to support efficient implementation of a wide range of real world ...
  • Determinism at standard-library level in TM-based applications 

    Smiljkovic, Vesna; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2017-02-01)
    Article
    Open Access
    Deterministic execution of a multi-threaded application guarantees that threads access shared memory in the same order and the application gives the same output whenever it runs with the same input parameters. Determinism ...
  • DeTrans: Deterministic and parallel execution of transactions 

    Smiljkovic, Vesna; Stipic, Srdjan; Fetzer, Christof; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
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    Deterministic execution of a multithreaded application guarantees the same output as long as the application runs with the same input parameters. Determinism helps a programmer to test and debug an application and to provide ...
  • Direct instruction wakeup for out-of-order processors 

    Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Veidenbaum, Alex; Villa, Luis A; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    Instruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. ...
  • DLP acceleration on general purpose cores 

    Duric, Milovan; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Barcelona Supercomputing Center, 2015-05-05)
    Conference report
    Open Access
    High-performance and power-efficient multimedia computing drives the design of modern and increasingly utilized mobile devices. State-of-the-art low power processors already utilize chip multiprocessors (CMP) that add ...
  • Dynamic transaction coalescing 

    Stipic, Srdjan; Karakostas, Vasileios; Smiljkovic, Vesna; Gajinov, Vladimir; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2014)
    Conference report
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    Prior work in Software Transactional Memory has identified high overheads related to starting and committing transactions that may degrade the application performance. To amortize these overheads, transaction coalescing ...
  • Dynamic-vector execution on a general purpose EDGE chip multiprocessor 

    Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug; Veidenbaum, Alexander V (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
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    This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector ...
  • EcoTM: Conflict-aware economical unbounded hardware transactional memory 

    Tomić, Saša; Akpinar, Ege; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (Elsevier, 2013)
    Conference report
    Open Access
    Transactional Memory (TM) is a promising paradigm for parallel programming. TM allows a thread to make a series of memory accesses as a single, atomic, transaction, while avoiding deadlocks, livelocks, and other problems ...
  • EMVS: Embedded Multi Vector-core System 

    Hussain, Tassadaq; Haider, Amna; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard (2018-06)
    Article
    Restricted access - publisher's policy
    With the increase in the density and performance of digital electronics, the demand for a power-efficient high-performance computing (HPC) system has been increased for embedded applications. The existing embedded HPC ...
  • Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi 

    Stanic, Milan; Palomar Pérez, Óscar; Ratkovic, Ivan; Duric, Milovan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    Graph500 is a data intensive application for high performance computing and it is an increasingly important workload because graphs are a core part of most analytic applications. So far there is no work that examines if ...
  • EVX: vector execution on low power EDGE cores 

    Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug (European Interactive Digital Advertising Alliance (EDAA), 2014)
    Conference report
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    In this paper, we present a vector execution model that provides the advantages of vector processors on low power, general purpose cores, with limited additional hardware. While accelerating data-level parallel (DLP) ...
  • Exploring the capabilities of support vector machines in detecting silent data corruptions 

    Subasi, Omer; Di, Sheng; Bautista-Gomez, Leonardo; Balaprakash, Prasanna; Unsal, Osman Sabri; Labarta Mancho, Jesús José; Cristal Kestelman, Adrián; Krishnamoorthy, Sriram; Cappello, Franck (Elsevier, 2018-09)
    Article
    Restricted access - publisher's policy
    As the exascale era approaches, the increasing capacity of high-performance computing (HPC) systems with targeted power and energy budget goals introduces significant challenges in reliability. Silent data corruptions ...
  • FaulTM: Error detection and recovery using hardware transactional memory 

    Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián (2013)
    Conference report
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    Reliability is an essential concern for processor designers due to increasing transient and permanent fault rates. Executing instruction streams redundantly in chip multi processors (CMP) provides high reliability since ...
  • FaulTM: Fault-tolerance using hardware transactional memory 

    Yalcin, Gulay; Unsal, Osman Sabri; Hur, Ibrahim; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2010)
    Conference report
    Open Access
    Fault-tolerance has become an essential concern for processor designers due to increasing soft-error rates. In this study, we are motivated by the fact that Transactional Memory (TM) hardware provides an ideal base upon ...
  • FIMSIM: A fault injection infrastructure for microarchitectural simulators 

    Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011)
    External research report
    Open Access
    Fault injection is a widely used approach for experiment-based dependability evaluation in which faults can be injected to the hardware, to the simulator or to the software. Simulation based fault injection is more appealing ...
  • From plasma to beefarm: Design experience of an FPGA-based multicore prototype 

    Sonmez, Nehir; Arcas Abella, Oriol; Sayilar, Gokhan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Singh, Satnam; Valero Cortés, Mateo (Springer, 2011)
    Conference report
    Open Access
    In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years ...