Exploració per autor "Rodríguez Montañés, Rosa"
Ara es mostren els items 21-40 de 43
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On the fitting and improvement of RRAM stanford-based model parameters using TiN/Ti/HfO2/W experimental data
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Comunicació de congrés
Accés restringit per política de l'editorialThe use of Resistive Random Access Memory (RRAM) devices is becoming pervasive in many applications. In particular, security based primitives can exploit their variability and non-volatility for generating cells for ... -
Post-Bond test of through-silicon vias with open defects
(2014)
Text en actes de congrés
Accés restringit per política de l'editorialThrough Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during ... -
Postbond test of through-silicon vias with resistive open defects
(2019-07-17)
Article
Accés obertThrough-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are ... -
Power-aware voltage tuning for STT-MRAM reliability
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialOne of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. ... -
Prebond testing of weak defects in TSVs
(2015-08-07)
Article
Accés restringit per política de l'editorialThrough-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process ... -
Programming techniques of resistive random-access memory devices for neuromorphic computing
(2023-11-27)
Article
Accés obertNeuromorphic computing offers a promising solution to overcome the von Neumann bottleneck, where the separation between the memory and the processor poses increasing limitations of latency and power consumption. For this ... -
Quiescent current analysis and experimentation of defective CMOS circuits
(1992-12)
Article
Accés restringit per política de l'editorialPhysical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. ... -
Random masking interleaved scrambling technique as a countermeasure for DPA/DEMA attacks in cache memories
(2016-11-15)
Text en actes de congrés
Accés obertMemory remanence in SRAMs and DRAMs is usually exploited through cold-boot attacks and the targets are the main memory and the L2 cache memory. Hence, a sudden power shutdown may give an attacker the opportunity to ... -
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialThe rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin- Transfer-Torque ... -
Reliability estimation at block-level granularity of spin-transfer-torque MRAMs
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialIn recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under ... -
Resistive open defect characteritzation in 3D 6T SRAM memories
(2014)
Text en actes de congrés
Accés restringit per política de l'editorialThe relentless decrease in feature size and the increase of density requirements in Integrated Circuit (IC) manufacturing arise new challenges that must be overcome. One of the most promising alternatives is three-dimensional ... -
RRAM based cell for hardware security applications
(2016)
Text en actes de congrés
Accés restringit per política de l'editorialResistive random access memories (RRAMs)have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. ... -
RRAM Based Random Bit Generation for Hardware Security Applications
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertResistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end ... -
RRAM random number generator based on train of pulses
(2021-07-30)
Article
Accés obertIn this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude ... -
Serial RRAM cell for secure bit concealing
(2021-07-31)
Article
Accés obertNon-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic ... -
Simulation of serial RRAM cell based on a Verilog-A compact model
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés restringit per política de l'editorialModel-based simulation is one of the effective methods of scientific research. The inherent variability of resistive switching mechanisms has been an obstacle for the massive commercial implementation of the resistive ... -
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialThe CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. ... -
Test escapes of stuck-open faults caused by parasitic capacitances and leakage currents
(2015-09-24)
Article
Accés obertIntragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled ... -
The low area probing detector as a countermeasure against invasive attacks
(2017-11-07)
Article
Accés obertMicroprobing allows intercepting data from on-chip wires as well as injecting faults into data or control lines. This makes it a commonly used attack technique against security-related semiconductors, such as smart card ... -
True random number generator based on RRAM-bias current starved ring oscillator
(Institute of Electrical and Electronics Engineers (IEEE), 2023-09-29)
Article
Accés obertThis work presents a RRAM-bias current starved ring oscillator (CSRO) as TRNG, where the cycle-to-cycle variability of a RRAM device is exploited as source of randomness. A simple voltage divider composed of this RRAM and ...
