Browsing by Author "Abella Ferrer, Jaume"
Now showing items 21-40 of 75
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FOCSI: A new layout regularity metric
(2009-06-09)
External research report
Open AccessDigital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ... -
Fuse: A technique to anticipate failures due to degradation in ALUs
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Conference report
Open AccessThis paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder ... -
Hardware/software-based diagnosis of load-store queues using expandable activity logs
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Conference report
Restricted access - publisher's policyThe increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing ... -
High-Performance low-vcc in-order core
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Conference report
Open AccessPower density grows in new technology nodes, thus requiring Vcc to scale especially in mobile platforms where energy is critical. This paper presents a novel approach to decrease Vcc while keeping operating frequency high. ... -
HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
Conference report
Open AccessHigh-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ... -
Implementing end-to-end register data-flow continuous self-test
(2011-08-01)
Article
Restricted access - publisher's policyWhile Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort ... -
Improving early design stage timing modeling in multicore based real-time systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessThis paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - ... -
Improving performance guarantees in wormhole mesh NoC designs
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessWormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates ... -
Improving time-randomized cache design
(Barcelona Supercomputing Center, 2018-04-24)
Conference report
Open AccessEnabling timing analysis for caches has been pursued by the critical real-time embedded systems (CRTES) community for years due to their potential to reduce worstcase execution times (WCET). Measurement-based protabilistic ... -
Inherently workload-balanced clustered microarchitecture
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Conference report
Open AccessThe performance of clustered microarchitectures relies on steering schemes that try to find the best trade-off between workload balance and inter-cluster communication penalties. In previously proposed clustered processors, ... -
Low-complexity distributed issue queue
(IEEE Computer Society, 2004)
Conference report
Open AccessAs technology evolves, power density significantly increases and cooling systems become more complex and expensive. The issue logic is one of the processor hotspots and, at the same time, its latency is crucial for the ... -
Low Vccmin fault-tolerant cache with highly predictable performance
(IEEE Press. Institute of Electrical and Electronics Engineers, 2009)
Conference report
Restricted access - publisher's policyTransistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent ... -
Measurement-based probabilistic timing analysis for multi-path programs
(2012)
Conference report
Restricted access - publisher's policyThe rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ... -
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyProbabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ... -
Measurement-based timing analysis of the AURIX caches
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
Conference report
Open AccessCache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ... -
Modeling high-performance wormhole NoCs for critical real-time embedded systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessManycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's ... -
Modelling probabilistic cache representativeness in the presence of arbitrary access patterns
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessMeasurement-Based Probabilistic Timing Analysis (MBPTA) is a promising powerful industry-friendly method to derive worst-case execution time (WCET) estimates as needed for critical real-time embedded systems. MBPTA performs ... -
Modelling the confidence of timing analysis for time randomised caches
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessTiming is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ... -
Multi-level unified caches for probabilistically time analysable real-time systems
(IEEEXPLORE, 2013)
Conference report
Restricted access - publisher's policyCaches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, ... -
Near-optimal loop tiling by means of cache miss equations and genetic algorithms
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Conference report
Open AccessThe effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ...
