Ara es mostren els items 21-40 de 212

    • Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification 

      Espinosa, Jaime; Hernandez, Carles; Abella Ferrer, Jaume; de Andres, David; Ruiz, Juan C. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated ...
    • APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation 

      Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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      Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown ...
    • Applying measurement-based probabilistic timing analysis to buffer resources 

      Kosmidis, Leonidas; Vardanega, Tulio; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2013)
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      The use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal ...
    • ASCOM: Affordable Sequence-aware COntention Modeling in crossbar-based MPSoCs 

      Giesen León, Jeremy Jens; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2023)
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      Multicore interference that arises when several accesses contend for the same shared hardware resources poses a challenge to the already demanding consolidated verification and validation practice. The Sequence-Aware Pairing ...
    • Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software Guidelines 

      Tabani, Hamid; Kosmidis, Leonidas; Abella Ferrer, Jaume; Cazorla, Francisco J.; Bernat, Guillem (Association for Computing Machinery (ACM), 2019-06-06)
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      The complexity and size of Autonomous Driving (AD) software are comparably higher than that of software implementing other (standard) functionalities in the car. To make things worse, a big fraction of AD software is not ...
    • At-scale evaluation of weight clustering to enable energy-efficient object detection 

      Caro, Martí; Tabani, Habani; Abella Ferrer, Jaume (Elsevier, 2022)
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      Accelerators implementing Deep Neural Networks (DNNs) for image-based object detection operate on large volumes of data due to fetching images and neural network parameters, especially if they need to process video streams, ...
    • AURIX TC277 Multicore Contention Model Integration for Automotive Applications 

      Mezzetti, Enrico; Barbina, Luca; Abella Ferrer, Jaume; Botta, Stefania; Cazorla, Francisco J. (IEEE, 2019-05-16)
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      The ability to produce early guaranteed performance (worst-case execution time) estimates for multicores, i.e. before software from different providers gets integrated onto the same critical system, is pivotal. This helps ...
    • Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story 

      Fuentes, Francisco; Alcaide Portet, Sergi; Casanova, Raimon; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2023)
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      Functional and performance validation of high-performance safety-related hardware platforms require generating specific traffic patterns in the network-on-chip (NoC) to test IP components and their integration. Software-only ...
    • Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis 

      Slijepcevic, Mladen; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2017-09-28)
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      Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical ...
    • Bus designs for time-probabilistic multicore processors 

      Jalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (European Interactive Digital Advertising Alliance (EDAA), 2014)
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      Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ...
    • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06-24)
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      Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...
    • Characterizing fault propagation in safety-critical processor designs 

      Espinosa, Jaime; Hernandez, Carles; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      Achieving reduced time-to-market in modern electronic designs targeting safety critical applications is becoming very challenging, as these designs need to go through a certification step that introduces a non-negligible ...
    • CleanET: enabling timing validation for complex automotive systems 

      Vilardell Moreno, Sergi; Serra Mochales, Isabel; Tabani, Hamid; Abella Ferrer, Jaume; del Castillo Franquet, Joan; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020)
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      Timing validation for automotive systems occurs in late integration stages when it is hard to control how the instances of software tasks overlap in time. To make things worse, in complex software systems, like those for ...
    • Compiler directed early register release 

      Jones, Timothy M.; O’Boyle, Michael F.P.; Abella Ferrer, Jaume; González Colás, Antonio María; Ergin, Oguz (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies registers that mil only be read once and renames ...
    • Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration 

      Fernandez, Gabriel; Jalle, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2016-10-11)
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      Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which ...
    • Computing worst-case contention delays for networks on chip 

      Cardona, Jordi; Hernandez, Carles; Abella Ferrer, Jaume (Barcelona Supercomputing Center, 2020-05)
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      Computing performance needs in domains such as automotive, avionics, railway, and space are on the rise. This is fueled by the trend towards implementing an increasing number of product functionalities in software that ...
    • Containing timing-related certification cost in automotive systems deploying complex hardware 

      Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Farrall, Glenn; Wartel, Franck; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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      Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ...
    • Contention in multicore hardware shared resources: Understanding of the state of the art 

      Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones, Eduardo; Rochange, Christine; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
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      The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ...
    • Contention tracking in GPU last-level cache 

      Barrera Herrera, Javier Enrique; Kosmidis, Leonidas; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2022)
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      The Last-level cache (LLC) is one of the main GPU’s shared resources that contributes to improve performance but also increases individual kernel’s performance variability. This is detrimental in scenarios in which some ...
    • Contention-aware performance monitoring counter support for real-time MPSoCs 

      Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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      Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ...