Now showing items 21-40 of 77

  • EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems 

    Cardona Nadal, Jordi; Abella Ferrer, Jaume; Hernández Luz, Carles; Cazorla Almeida, Francisco Javier (2018-07-17)
    Article
    Open Access
    The increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ...
  • Evolutionary system for prediction and optimization of hardware architecture performance 

    Castillo, Pedro Angel; Merelo, Juan Julián; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally (2008-06)
    Conference report
    Open Access
    The design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ...
  • Fitting processor architectures for measurement-based probabilistic timing analysis 

    Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Hernández, Carles; Gianarro, Andrea; Broster, Ian; Cazorla Almeida, Francisco Javier (2016-11-01)
    Article
    Open Access
    The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case ...
  • HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems 

    Benedicte Illescas, Pedro; Hernandez, C.; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
    Conference report
    Open Access
    High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ...
  • Implicit vs. explicit resource allocation in SMT processors 

    Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Garcia, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    In a simultaneous multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among the threads. In this paper, we describe ...
  • Improving early design stage timing modeling in multicore based real-time systems 

    Trilla, David; Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - ...
  • Improving performance guarantees in wormhole mesh NoC designs 

    Panic, Milos; Hernández, Carles; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Wormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates ...
  • Improving time-randomized cache design 

    Benedicte Illescas, Pedro; Hernández Gañán, Carlos; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2018-04-24)
    Conference report
    Open Access
    Enabling timing analysis for caches has been pursued by the critical real-time embedded systems (CRTES) community for years due to their potential to reduce worstcase execution times (WCET). Measurement-based protabilistic ...
  • Increasing multicore system efficiency through intelligent bandwidth shifting 

    Jiménez, Víctor; Buyuktosunoglu, Alper; Bose, Pradip; O'Connell, Francis P.; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Restricted access - publisher's policy
    Memory bandwidth is a crucial resource in computing systems. Current CMP/SMT processors have a significant number of cores and they can run many threads concurrently. This large thread count adds high pressure to the memory ...
  • ITCA: Inter-Task Conflict-Aware CPU accounting for CMP 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Valero Cortés, Mateo (2010)
    Conference report
    Open Access
    Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
  • ITCA: inter-task conflict-aware CPU accounting for CMPs 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (IEEE Computer Society Publications, 2009)
    Conference report
    Restricted access - publisher's policy
  • Locality-aware cache random replacement policies 

    Benedicte Illescas, Pedro; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Elsevier, 2019-02)
    Article
    Restricted access - publisher's policy
    Measurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ...
  • Maximizing multithreaded multicore architectures through thread migrations 

    Acosta Ojeda, Carmelo Alexis; Cazorla Almeida, Francisco Javier; Santana Jaria, Oliverio J.; Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009)
    External research report
    Open Access
    Heterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a ...
  • Measurement-based probabilistic timing analysis for multi-path programs 

    Cucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2012)
    Conference report
    Restricted access - publisher's policy
    The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ...
  • Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study 

    Wartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
  • Measurement-based timing analysis of the AURIX caches 

    Kosmidis, Leonidas; Compagnin, Davide; Morales, David; Mezzetti, Enrico; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
    Conference report
    Open Access
    Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ...
  • Measuring operating system overhead on CMT processors 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (IEEE Computer Society Publications, 2008)
    Conference report
    Open Access
    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ...
  • Measuring operating system overhead on Sun UltraSparc T1 processor 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2009-06)
    Conference report
    Open Access
    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ...
  • MFLUSH: handling long-latency loads in SMT on-chip multiprocessors 

    Acosta Ojeda, Carmelo Alexis; Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (IEEE Computer Society Publications, 2008)
    Conference report
    Open Access
    Nowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores (CMP), where each core is Simultaneous Multithreading (SMT). State-of-the-art ...
  • MLP-aware dynamic cache partitioning 

    Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Conference lecture
    Open Access
    The limitation imposed by instruction-level parallelism (ILP) has motivated the use of thread-level parallelism (TLP) as a common strategy for improving processor performance. TLP paradigms such as simultaneous multithreading ...