Exploració per autor "Cazorla Almeida, Francisco Javier"
Ara es mostren els items 21-40 de 145
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CleanET: enabling timing validation for complex automotive systems
Vilardell Moreno, Sergi; Serra Mochales, Isabel; Tabani, Hamid; Abella Ferrer, Jaume; del Castillo Franquet, Joan; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020)
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Accés obertTiming validation for automotive systems occurs in late integration stages when it is hard to control how the instances of software tasks overlap in time. To make things worse, in complex software systems, like those for ... -
Containing timing-related certification cost in automotive systems deploying complex hardware
Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Farrall, Glenn; Wartel, Franck; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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Accés restringit per política de l'editorialMeasurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ... -
Contention in multicore hardware shared resources: Understanding of the state of the art
Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones, Eduardo; Rochange, Christine; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
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Accés obertThe real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ... -
Contention tracking in GPU last-level cache
Barrera Herrera, Javier Enrique; Kosmidis, Leonidas; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2022)
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Accés obertThe Last-level cache (LLC) is one of the main GPU’s shared resources that contributes to improve performance but also increases individual kernel’s performance variability. This is detrimental in scenarios in which some ... -
Contention-aware performance monitoring counter support for real-time MPSoCs
Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Comunicació de congrés
Accés obertTasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ... -
Data bus slicing for contention-free multicore real-time memory systems
Jalle Ibarra, Javier; Quiñones, Eduardo; Abella Ferrer, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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Accés obertMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ... -
Dcache Warn: an I-fetch policy to increase SMT efficiency
Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Garcia, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
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Accés obertSimultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, ... -
Deconstructing bus access control policies for real-time multicores
Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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Accés restringit per política de l'editorialMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ... -
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems
Asifuzzaman, Kazi; Abuelala, Mohamed; Hassan, Mohamed; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2021-12)
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Accés obertThe number of functionalities controlled by software on every critical real-time product is on the rise in domains like automotive, avionics and space. To implement these advanced functionalities, software applications ... -
Design and integration of hierarchical-placement multi-level caches for real-Time systems
Benedicte Illescas, Pedro; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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Accés restringit per política de l'editorialEnabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ... -
DReAM: An approach to estimate per-Task DRAM energy in multicore systems
Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2016-12)
Article
Accés obertAccurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ... -
DReAM: Per-task DRAM energy metering in multicore systems
Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Springer, 2014)
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Accés obertInteraction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ... -
DTM: degraded test mode for fault-aware probabilistic timing analysis
Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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Accés restringit per política de l'editorialExisting timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ... -
Dynamic and execution views to improve validation, testing, and optimization of autonomous driving software
Alcón Doganoc, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Springer Nature, 2023-06)
Article
Accés obertThe adoption of autonomous driving (AD) software executed on high-performance multi-processor systems on chip (MPSoCs) contributes to increasing the overall system’s safety and efficiency. However, existing AD software ... -
Dynamically controlled resource allocation in SMT processors
Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Prieto, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
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Accés obertSMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for ... -
Empirical evidence for MPSoCs in critical systems: The case of NXP’s T2080 cache coherence
Pujol Torramorell, Roger; Tabani, Hamid; Abella Ferrer, Jaume; Hassan, Mohamed; Cazorla Almeida, Francisco Javier (IEEE, 2021)
Comunicació de congrés
Accés obertThe adoption of complex MPSoCs in critical real-time embedded systems mandates a detailed analysis their architecture to facilitate certification. This analysis is hindered by the lack of a thorough understanding of the ... -
En-route: on enabling resource usage testing for autonomous driving frameworks
Alcon, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Kosmidis, Leonidas; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020-03)
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Accés obertSoftware resource usage testing, including execution time bounds and memory, is a mandatory validation step during the integration of safety-related real-time systems. However, the inherent complexity of Autonomous Driving ... -
Enabling SMT for real-time embedded systems
Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
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Accés obertIn order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ... -
Enabling unit testing of already-integrated AI software systems: The case of Apollo for autonomous driving
Alcón Doganoc, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2021)
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Accés obertThe advanced AI-based software used for autonomous driving comprises multiple highly-coupled modules that are data and control dependent. Deploying those already-integrated software frameworks makes unit testing, a fundamental ... -
EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems
Cardona Nadal, Jordi; Abella Ferrer, Jaume; Hernández Luz, Carles; Cazorla Almeida, Francisco Javier (2018-07-17)
Article
Accés obertThe increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ...