Exploració per autor "Rubio Sola, Jose Antonio"
Ara es mostren els items 21-40 de 175
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Advanced failure detection techniques in deep submicron CMOS integrated circuits
(Pergamon Press, 2009)
Text en actes de congrés
Accés restringit per política de l'editorialThe test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability ... -
Alternative memristor-based interconnect topologies for fast adaptive synchronization of chaotic circuits
(2020-09)
Article
Accés obertResistive switching devices (memristors) constitute an emerging device technology promising for a vari- ety of applications that are currently being studied. In this context, the use of memristors as coupling el- ements ... -
An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
An approach to dynamic power consumption current testing of CMOS ICs
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertI/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can ... -
An on-line test strategy and analysis for a 1T1R crossbar memory
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertMemristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ... -
Analysis and modelling of parasitic substrate coupling in CMOS circuits
(1995-10)
Article
Accés restringit per política de l'editorialAnalysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ... -
Analysis of body bias and RTN-induced frequency shift of low voltage ring oscillators in FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialElectronic circuits powered at ultra low voltages (500 mV and below) are desirable for their low energy and power consumption. However, RTN (Random Telegraph Noise)-induced threshold voltage variations become very significant ... -
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations
(IEEE, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialEnvironmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity ... -
Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertDifference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design ... -
Análisis del retardo en enlaces con protocolos ARQ y control de flujo: aplicación a una red estrella
(Marcombo, 1983)
Text en actes de congrés
Accés obertEl objetivo de este trabajo se enmarca en el desarrollo de herramientas de cuantificación de los tiempos de retardo en redes de computadores. El análisis se ha centrado en la evaluación del tiempo medio de retardo en el ... -
Asynchronous pulse logic cell for threshold logic and Boolean networks
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés restringit per política de l'editorialIn this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ... -
Beneficial role of noise in Hf-based memristors
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe beneficial role of noise in the performance of Hf-based memristors has been experimentally studied. The addition of an external gaussian noise to the bias circuitry positively impacts the memristors characteristics by ... -
Carbon nanotube growth process-related variablity in CNFET's
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialIn silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. Novel nanoscale beyond- CMOS devices are being studied such as carbon ... -
CBRAM-based bio-inspired circuit for the emulation and treatment of the Parkinson’s Disease
(2023-12-05)
Article
Accés restringit per decisió de l'autorIn recent years, the intrinsic neuromorphic properties of memristor devices have led to their extensive use in brain-inspired circuits and systems. The development of brain-inspired (nano)circuits incorporating memristors ... -
Characterization of random telegraph noise and its impact on reliability of SRAM sense amplifiers
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertA new method for the analysis of multilevel Random Telegraph Noise (RTN) signals has been recently presented, which can also be applied in the case of large background noise. In this work, the method is extended to evaluate ... -
Characterization of the substrate noise spectrum for mixed-signal ICs
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertThis paper presents a simplified analytical model of the substrate noise generated by digital circuitry that captures the most relevant frequency domain characteristics and relates them with parameters of the digital circuit ... -
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialWith every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ... -
Circuit topology and synthesis flow co-design for the development of computational ReRAM
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertEmerging memory technologies will play a decisive role in the quest for more energy-efficient computing systems. Computational ReRAM structures based on resistive switching devices (memristors) have been explored for ... -
Compact thermo-diffusion based physical memristor model
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés restringit per política de l'editorialThe threshold switching effect is critical in memristor devices for a range of applications, from crossbar design reliability to simulating neuromorphic features using artificial neural networks. The rich inherit dynamics ... -
Controlled degradation stochastic resonance in adaptive averaging cell-based architectures
(2013-11)
Article
Accés restringit per política de l'editorialIn this paper, we first analyze the degradation stochastic resonance (DSR) effect in the context of adaptive averaging (AD-AVG) architectures. The AD-AVG is the adaptive version of the well-known AVG architecture . It is ...
