Exploració per altres contribucions "Valero Cortés, Mateo"

Ara es mostren els items 21-39 de 39

    • On the analysis of the timing behaviour of time randomised caches 

      Benedicte Illescas, Pedro (Universitat Politècnica de Catalunya, 2016-07-07)
      Projecte Final de Màster Oficial
      Accés obert
      Time Randomised caches (TRc), which can be implemented at hardware level or with software means on conventional deterministic cache designs, have been proposed for real-time systems as key enablers for Probabilistic ...

    • On the design of power- and energy-efficient functional units for vector processors 

      Ratkovic, Ivan (Universitat Politècnica de Catalunya, 2016-12-14)
      Tesi
      Accés obert
      Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting datalevel parallelism. While vector processors succeeded in the high performance ...

    • Optimizing VLIW architectures for multimedia applications 

      Salamí San Juan, Esther (Universitat Politècnica de Catalunya, 2007-06-01)
      Tesi
      Accés obert
      The growing interest that multimedia processing has experimented during the last decade is motivating processor designers to reconsider which execution paradigms are the most appropriate for general-purpose processors. On ...

    • Parallel video decoding 

      Álvarez Mesa, Mauricio (Universitat Politècnica de Catalunya, 2011-09-08)
      Tesi
      Accés obert
      Digital video is a popular technology used in many different applications. The quality of video, expressed in the spatial and temporal resolution, has been increasing continuously in the last years. In order to reduce the ...

    • Parallelization techniques of the x264 video encoder 

      Ruiz Muñoz, Daniel (Universitat Politècnica de Catalunya, 2014-06-20)
      Projecte/Treball Final de Carrera
      Accés obert
      [CASTELLÀ] Aquest projecte consisteix en portar el codificador de video x264 que es troba a la suite de benchmarks PARSEC utilitzant el model de promació OmpSs. Per fer això haurem d'avaluar el rendiment de les versions ...

    • Per-task energy metering and accounting in the multicore era 

      Liu, Qixiao (Universitat Politècnica de Catalunya, 2016-05-26)
      Tesi
      Accés obert
      Chip multi-core processors (CMPs) are the preferred processing platform across different domains such as data centers, real-time systems and mobile devices. In all those domains, energy is arguably the most expensive ...

    • Performance and power optimizations in chip multiprocessors for throughput-aware computation 

      Vega, Augusto J. (Universitat Politècnica de Catalunya, 2013-07-30)
      Tesi
      Accés obert
      The so-called "power (or power density) wall" has caused core frequency (and single-thread performance) to slow down, giving rise to the era of multi-core/multi-thread processors. For example, the IBM POWER4 processor, ...

    • Power Models for Multicore Processor Simulators with Multiple Levels of Abstraction 

      Triviño Valls, Josep (Universitat Politècnica de Catalunya, 2015-06-30)
      Treball Final de Grau
      Accés obert
      En aquest projecte he creat una eina capaç de generar models energètics per diferents aplicacions donat un hardware determinat. Amb aquesta eina, es pot obtenir el consum energètic total de qualsevol aplicació i dels ...

    • Programming, debugging, profiling and optimizing transactional memory programs 

      Hasanov Zyulkyarov, Ferard (Universitat Politècnica de Catalunya, 2011-07-19)
      Tesi
      Accés obert
      Transactional memory (TM) is a new optimistic synchronization technique which has the potential of making shared memory parallel programming easier compared to locks without giving up from the performance. This thesis ...

    • Raising the level of abstraction : simulation of large chip multiprocessors running multithreaded applications 

      Rico Carro, Alejandro (Universitat Politècnica de Catalunya, 2013-10-29)
      Tesi
      Accés obert
      The number of transistors on an integrated circuit keeps doubling every two years. This increasing number of transistors is used to integrate more processing cores on the same chip. However, due to power density and ILP ...

    • Recursos anchos: una técnica de bajo coste para explotar paralelismo agresivo en códigos numéricos 

      López Álvarez, David (Universitat Politècnica de Catalunya, 1998-12-15)
      Tesi
      Accés obert
      Els bucles son la part que més temps consumeix en les aplicacions numèriques. El rendiment dels bucles està limitat tant pels recursos oferts per l'arquitectura com per les recurrències del bucle en la computació. ...

    • Runahead threads 

      Ramírez García, Tanausu (Universitat Politècnica de Catalunya, 2010-04-15)
      Tesi
      Accés obert
      Los temas de investigación sobre multithreading han ganado mucho interés en la arquitectura de computadores con la aparición de procesadores multihilo y multinucleo. Los procesadores SMT (Simultaneous Multithreading) son ...

    • Runtime assisted cache memory optimizations 

      Dimic, Vladimir (Universitat Politècnica de Catalunya, 2015-07-09)
      Projecte Final de Màster Oficial
      Accés restringit per acord de confidencialitat

    • Scalable system software for high performance large-scale applications 

      Morari, Alessadro (Universitat Politècnica de Catalunya, 2014-05-27)
      Tesi
      Accés obert
      In the last decades, high-performance large-scale systems have been a fundamental tool for scientific discovery and engineering advances. The sustained growth of supercomputing performance and the concurrent reduction in ...

    • Software support to strengthen measurement-based timing analysis 

      Díaz Roque, Enrique (Universitat Politècnica de Catalunya, 2017-07)
      Projecte Final de Màster Oficial
      Accés obert
      In critical domains, the advent of high-performance (complex) hardware, used to provide the rising levels of guaranteed performance, complicates providing evidence of reliable software execution specially on aspects ...

    • Specialization and reconfiguration of lightweight mobile processors for data-parallel applications 

      Duric, Milovan (Universitat Politècnica de Catalunya, 2016-01-26)
      Tesi
      Accés obert
      The worldwide utilization of mobile devices makes the segment of low power mobile processors leading in the entire computer industry. Customers demand low-cost, high-performance and energy-efficient mobile devices, which ...

    • Techniques for improving the performance of software transactional memory 

      Stipić, Srđan (Universitat Politècnica de Catalunya, 2014-07-21)
      Tesi
      Accés obert
      Transactional Memory (TM) gives software developers the opportunity to write concurrent programs more easily compared to any previous programming paradigms and gives a performance comparable to lock-based synchronization ...

    • Tècniques de paral·lelització del simulador Facesim 

      Vidal Ortiz, Raul (Universitat Politècnica de Catalunya, 2015-01-26)
      Treball Final de Grau
      Accés obert
      [CASTELLÀ] Este proyecto hace una evaluación de OmpSs como tecnología para entornos de centros de datos en busca de mejoras en el mantenimiento de aplicaciones así como su eficiencia y costes. Facesim ha sido utilizada ...

    • Vector architectures for Exascale 

      Caminal Pallarés, Helena (Universitat Politècnica de Catalunya, 2017-07-03)
      Projecte Final de Màster Oficial
      Accés restringit per acord de confidencialitat