Exploració per autor "Valero Cortés, Mateo"
Ara es mostren els items 21-40 de 357
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A scalable synthetic traffic model of Graph500 for computer networks analysis
(2017-12-25)
Article
Accés obertThe Graph500 benchmark attempts to steer the design of High-Performance Computing systems to maximize the performance under memory-constricted application workloads. A realistic simulation of such benchmarks for architectural ... -
A simulation framework to automatically analyze the communication-computation overlap in scientific applications
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés obertOverlapping communication and computation has been devised as an attractive technique to alleviate the huge application's network requirements at large scale. Overlapping will allow to fully or partially hide the long ... -
A systolic algorithm for the fast computation of the connected components of a graph
(Institute of Electrical and Electronics Engineers (IEEE), 1988)
Text en actes de congrés
Accés obertThe authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. ... -
A two level load/store queue based on execution locality
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Text en actes de congrés
Accés obertMulticore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ... -
A vector-µSIMD-VLIW architecture for multimedia applications
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertMedia processing has motivated strong changes in the focus and design of processors. These applications are composed of heterogeneous regions of code, some of them with high levels of DLP and other ones with only modest ... -
A vulnerability factor for ECC-protected memory
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertFault injection studies and vulnerability analyses have been used to estimate the reliability of data structures in memory. We survey these metrics and look at their adequacy to describe the data stored in ECC-protected ... -
Access to streams in multiprocessor systems
(Institute of Electrical and Electronics Engineers (IEEE), 1993)
Text en actes de congrés
Accés obertWhen accessing streams in vector multiprocessor machines, degradation in the interconnection network and conflicts in the memory modules are the factors that reduce the efficiency of the system. In this paper, we present ... -
Access to vectors in multi-module memories
(Institute of Electrical and Electronics Engineers (IEEE), 1994)
Text en actes de congrés
Accés obertThe poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnection network degrades the performance of computers. Address transformation schemes, such as interleaving, skewing and linear ... -
ADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches
(2012)
Text en actes de congrés
Accés restringit per política de l'editorialSemiconductor technology evolution enables the design of ultra-low-cost chips (e.g., below 1 USD) required for new market segments such as environment, urban life and body monitoring, etc. Recently, hybrid-operation (high ... -
Adaptable register file organization for vector processors
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertContemporary Vector Processors (VPs) are de-signed either for short vector lengths, e.g., Fujitsu A64FX with 512-bit ARM SVE vector support, or long vectors, e.g., NEC Aurora Tsubasa with 16Kbits Maximum Vector Length ... -
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés obertRecent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least ... -
Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7
(2015)
Text en actes de congrés
Accés obert -
Advanced pattern based memory controller for FPGA based HPC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialThe ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ... -
Advances in the Hierarchical Emergent Behaviors (HEB) approach to autonomous vehicles
(2020)
Article
Accés obertWidespread deployment of autonomous vehicles (AVs) presents formidable challenges in terms on handling scalability and complexity, particularly regarding vehicular reaction in the face of unforeseen corner cases. Hierarchical ... -
Align and distribute-based linear loop transformations
(Springer, 1993)
Text en actes de congrés
Accés obertIn this paper we generalize the framework of linear loop transformations in the sense that loop alignment is considered as a new component in the transformation process. The aim is to match the structure of loop nests with ... -
Alya: Multiphysics engineering simulation toward exascale
(Elsevier, 2016-02-01)
Article
Accés obertAlya is a multi-physics simulation code developed at Barcelona Supercomputing Center (BSC). From its inception Alya code is designed using advanced High Performance Computing programming techniques to solve coupled problems ... -
Alya: Multiphysics engineering simulation toward exascale
(Elsevier, 2016-05)
Article
Accés obertAlya is a multi-physics simulation code developed at Barcelona Supercomputing Center (BSC). From its inception Alya code is designed using advanced High Performance Computing programming techniques to solve coupled problems ... -
AMMC: advance multi-core memory controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Comunicació de congrés
Accés obertIn this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ... -
An abstraction methodology for the evaluation of multi-core multi-threaded architectures
(IEEE Computer Society Publications, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialAs the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ... -
An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...
