Exploració per autor "Salami, Behzad"
Ara es mostren els items 21-24 de 24
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On the resilience of deep learning for reduced-voltage FPGAs
Givaki, Kamyar; Salami, Behzad; Hojabr, Reza; Tayaranian, S. M. Reza; Khonsari, Ahmad; Rahmati, Dara; Gorgin, Saeid; Cristal Kestelman, Adrián; Unsal, Osman Sabri (Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertDeep Neural Networks (DNNs) are inherently computation-intensive and also power-hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a promising solution that can satisfy these requirements for ... -
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation
Salami, Behzad; Unsal, Osman S.; Cristal Kestelman, Adrián (IEEE, 2019-02-21)
Comunicació de congrés
Accés obertMachine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute and power-intensive structure ... -
Towards resilient EU HPC systems: A blueprint
Radojković, Petar; Marazakis, Manolis; Carpenter, Paul Matthew; Jeyapaul, Reiley; Gizopoulos, Dimitris; Schulz, Martin; Armejach Sanosa, Adrià; Ayguadé Parra, Eduard; Canal Corretger, Ramon; Moretó Planas, Miquel; Salami, Behzad; Unsal, Osman Sabri (2020-04)
Report de recerca
Accés obertThis document aims to spearhead a Europe-wide discussion on HPC system resilience and to help the European HPC community define best practices for resilience. We analyse a wide range of state-of-the-art resilience mechanisms ... -
Understanding power consumption and reliability of high-bandwidth memory with voltage underscaling
Nabavilarimi, Seyed Saber; Salami, Behzad; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Sarbazi-Azad, Hamid; Mutlu, Onur (Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertModern computing devices employ High-Bandwidth Memory (HBM) to meet their memory bandwidth requirements. An HBM-enabled device consists of multiple DRAM layers stacked on top of one another next to a compute chip (e.g, ...