Now showing items 21-40 of 112

  • Asynchronous pulse logic cell for threshold logic and Boolean networks 

    Lambie, J; Moll Echeto, Francisco de Borja; González Jiménez, José Luis; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Restricted access - publisher's policy
    In this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ...
  • Carbon nanotube growth process-related variablity in CNFET's 

    García Almudéver, Carmen; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Conference report
    Restricted access - publisher's policy
    In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. Novel nanoscale beyond- CMOS devices are being studied such as carbon ...
  • Characterization of random telegraph noise and its impact on reliability of SRAM sense amplifiers 

    Martín Martínez, Javier; Diaz, Javier; Rodríguez, Rosana; Nafria, Montse; Aymerich Humet, Xavier; Roca Moreno, Elisenda; Fernández Fernández, Francisco V.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    A new method for the analysis of multilevel Random Telegraph Noise (RTN) signals has been recently presented, which can also be applied in the case of large background noise. In this work, the method is extended to evaluate ...
  • Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Conference report
    Restricted access - publisher's policy
    With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ...
  • Controlled degradation stochastic resonance in adaptive averaging cell-based architectures 

    Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (2013-11)
    Article
    Restricted access - publisher's policy
    In this paper, we first analyze the degradation stochastic resonance (DSR) effect in the context of adaptive averaging (AD-AVG) architectures. The AD-AVG is the adaptive version of the well-known AVG architecture . It is ...
  • Converses sobre disseny digital: dubtes a l'hora de fer una simulació 

    Altet Sanahujes, Josep; Rubio Sola, Jose Antonio; Bardés Llorensí, Daniel; Calderer Cardona, Josep; Pons Nin, Joan; Mateo Peña, Diego; Martín, Isidro (Departament d'Enginyeria Electrònica, 2016-10-25)
    Audiovisual
    Open Access
  • Coupled physarum-inspired memristor oscillators for neuron-like operations 

    Ntinas, Vasileios; Vourkas, Ioannis; Sirakoulis, Georgios Ch.; Adamatzky, Andrew; Rubio Sola, Jose Antonio (2018)
    Conference report
    Open Access
    Unconventional computing has been studied intensively, even after the appearance of CMOS technology. Currently, it has returned to the spotlight because CMOS is about to reach its physical limits, given that the constant ...
  • Crossbar-based memristive logic-in-memory architecture 

    Papandroulikadis, Georgios; Vourkas, Ioannis; Abustelema, Angel; Sirakoulis, Georgios; Rubio Sola, Jose Antonio (2017-04-01)
    Article
    Open Access
    The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the ...
  • Cross-talk extraction from mask layout 

    Sicard, E.; Demonchaux, T.; Noullet, J.L.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Conference report
    Restricted access - publisher's policy
    The principles of an automated cross-talk extractor from the mask-level description of a CMOS integrated circuit are detailed. The physical extraction principles, the techniques for parasitic coupling evaluation and modeling, ...
  • Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches 

    Pouyan, Peyman; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
    Conference report
    Restricted access - publisher's policy
    Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design techniques for improving the circuit robustness. This work proposes an implementation of adaptive proactive reconfiguration ...
  • Design guidelines towards compact litho-friendly regular cells 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Elhoj, Martin; Schlinker, Guilherme; Woolaway, Nigel (2011)
    Conference report
    Open Access
  • Design of complex circuits using the via-configurable transistor array regular layout fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
    Conference report
    Restricted access - publisher's policy
    Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...
  • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-04-15)
    External research report
    Open Access
    In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.
  • Effectiveness of hybrid recovery techniques on parametric failures 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    Modern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V ddmin. On-chip memories like caches ...
  • Eines d’autor: avaluació de noves eines orientades al desenvolupament de competències genèriques per la millora del procés d’aprenentatge autònom dels estudiants 

    Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Vigara Campmany, Julio Enrique; Romeral Martínez, José Luis; Ortega Redondo, Juan Antonio (Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2013-02-08)
    Conference report / Conference lecture
    Open Access
    Els cursos on-line massius (Massive Open On-line Courses) estan emergent i suposarà un gran repte en l’educació universitària en els propers anys. Universitats com Standford i MIT han començat aquest any cursos en obert ...
  • Error probability in synchronous digital circuits due to power supply noise 

    Martorell Cid, Ferran; Pons, M; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja (???, 2007)
    Conference report
    Open Access
    This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered ...
  • Experience on material implication computing with an electromechanical memristor emulator 

    Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Escudero López, Manuel; Zuin, Stefano; Vourkas, Ioannis; Sirakoulis, Georgios (IEEE Press, 2016)
    Conference report
    Open Access
    Memristors are being considered as a promising emerging device able to introduce new paradigms in both data storage and computing. In this paper the authors introduce the concept of a quasi-ideal experimental device that ...
  • Experimental study of artificial neural networks using a digital memristor simulator 

    Ntinas, Vasileios; Vourkas, Ioannis; Abusleme, Angel; Sirakoulis, Georgios; Rubio Sola, Jose Antonio (2018-02-01)
    Article
    Open Access
    This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog ...
  • Experimental time evolution study of the HFO-based IMPLY gate operation 

    Maestro, M; Marin-Martinez, J.; Crespo-Yepes, A.; Escudero, Manel; Rodriguez, R.; Nafria, M.; Aymerich, X.; Rubio Sola, Jose Antonio (2018-02-01)
    Article
    Open Access
    In the last years, memristor devices have been proposed as key elements to develop a new paradigm to implement logic gates. In particular, the memristor-based material implication (IMPLY) gate has been presented as a ...
  • Experimental verification of memristor-based material implication NAND operation 

    Maestro Izquierdo, Marcos; Martin Martínez, Javier; Crespo Yepes, Albert; Escudero López, Manuel; Rodríguez Martínez, Rosana; Nafría Maqueda, Montserrat; Aymerich Humet, Xavier; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017-10-11)
    Article
    Open Access
    Memristors are being considered as promising devices for highly dense memory systems as well as the potential basis of new computational paradigms. In this scenario, and in relation with data processing, one of the more ...