Now showing items 21-40 of 170

    • An asynchronous architecture model for behavioral synthesis 

      Cortadella, Jordi; Badia Sala, Rosa Maria (Institute of Electrical and Electronics Engineers (IEEE), 1993)
      Conference report
      Open Access
      An asynchronous architecture model for behavioral synthesis is presented. The basis of the model lies in a distributed control structure consisting of multiple communicating processes. Data processing is performed by ...
    • An efficient unique state coding algorithm for signal transition graphs 

      Pastor Llorens, Enric; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1993)
      Conference report
      Open Access
      Current algorithms to force the complete state coding (CSC) property for signal transition graphs work on the state graph and, therefore require exponential time and space. Polynomial algorithms have been only proposed for ...
    • Architectural exploration of large-scale hierarchical chip multiprocessors 

      Nikitin, Nikita; San Pedro Martín, Javier de; Cortadella, Jordi (2013)
      Article
      Restricted access - publisher's policy
      The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more ...
    • Area-optimal transistor folding for 1-D gridded cell design 

      Cortadella, Jordi (2013-11)
      Article
      Open Access
      The 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which ...
    • Asynchronous interface specification, analysis and synthesis 

      Kishinewsky, M; Cortadella, Jordi; Kondratyev, A; Lavagno, L (1998-03)
      External research report
      Open Access
      Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed modules/agents without common clock. However, recent development in theory of asynchronous design in the area of ...
    • Asynchronous multipliers with variable-delay counters 

      Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
      Conference report
      Open Access
      Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are available, it still represents one of the major bottlenecks of many digital systems that require intensive ...
    • Automatic generation of synchronous test patterns for asynchronous circuits 

      Roig Mansilla, Oriol; Cortadella, Jordi; Peña Basurto, Marco Antonio; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 1997)
      Conference report
      Open Access
      This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, ...
    • Automatic microarchitectural pipelining 

      Galcerán Oms, Marc; Cortadella, Jordi; Bufistov, Dmitry; Kishinevsky, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Conference report
      Open Access
      This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous ...
    • Automatic synthesis and optimization of partially specified asynchronous systems 

      Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Lavagno, Luciano; Yakovlev, Alex (Association for Computing Machinery (ACM), 1999)
      Conference report
      Open Access
      A method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key ...
    • Automating synthesis of asynchronous communication mechanisms 

      Cortadella, Jordi; Costa Gorgônio, Kyller; Xia, Fei; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 2005)
      Conference report
      Open Access
      Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed processes in digital systems. In previous work, systematic ACM synthesis methods have been ...
    • Behavioral transformations to increase the noise immunity of asynchronous specifications 

      Taubin, Alexander; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 1999)
      Conference report
      Open Access
      Noise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originated by simultaneous switching ...
    • Boolean decomposition for AIG optimization 

      Machado, Lucas; Cortadella, Jordi (Association for Computing Machinery (ACM), 2017)
      Conference report
      Open Access
      Restructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the ...
    • Boolean decomposition using two-literal divisors 

      Modi, Nilesh A.; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Conference report
      Open Access
      This paper is an attempt to answer the following question: how much improvement can be obtained in logic decomposition by using Boolean divisors? Traditionally, the existence of too many Boolean divisors has been the main ...
    • Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis 

      Saito, Hiroshi; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1999)
      Conference report
      Open Access
      Two trends are of major concern for digital circuit designers: the relative increase of interconnect delays with respect to gate delays and the demand for design reuse. Both pose difficult problems to synchronous design ...
    • CAD directions for high performance asynchronous circuits 

      Stevens, Kenneth S.; Rotem, Shai; Burns, Steven M.; Cortadella, Jordi; Ginosar, Ran; Kishinevsky, Michael; Roncken, Marly (Association for Computing Machinery (ACM), 1999)
      Conference report
      Open Access
      This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ...
    • Checking signal transition graph implementability by symbolic bdd traversal 

      Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Pastor Llorens, Enric; Roig Mansilla, Oriol; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1995)
      Conference report
      Open Access
      This paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification ...
    • Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits 

      Peña Basurto, Marco Antonio; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1996)
      Conference report
      Open Access
      This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic ...
    • Combining structural and symbolic methods for the verification of concurrent systems 

      Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1998)
      Conference report
      Open Access
      The contributions during the last few years on the structural theory of Petri nets can now be applied to formal verification. The structural theory provides methods to find efficient encoding schemes for symbolic representations ...
    • Complete state encoding based on the theory of regions 

      Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1996)
      Conference report
      Open Access
      Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which ...
    • Coping with the variability of combinational logic delays 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Conference report
      Open Access
      This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ...