Now showing items 21-40 of 335

  • A general guide to applying machine learning to computer architecture 

    Nemirovsky, Daniel; Arkose, Tugberk; Markovic, Nikola; Nemirovsky, Mario; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2018)
    Article
    Open Access
    The resurgence of machine learning since the late 1990s has been enabled by significant advances in computing performance and the growth of big data. The ability of these algorithms to detect complex patterns in data which ...
  • A hardware runtime for task-based programming models 

    Tan, Xubin; Bosch, Jaume; Álvarez, Carlos; Jiménez González, Daniel; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2019-09-01)
    Article
    Open Access
    Task-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only ...
  • A highly scalable parallel implementation of H.264 

    Azevedo, Arnaldo; Juurlink, Ben; Meenderinck, Cor; Terechko, Andrei; Hoogerbrugge, Jan; Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2011)
    Article
    Open Access
    Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation ...
  • A low-complexity, high-performance fetch unit for simultaneous multithreading processors 

    Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    Simultaneous multithreading (SMT) is an architectural technique that allows for the parallel execution of several threads simultaneously. Fetch performance has been identified as the most important bottleneck for SMT ...
  • Alya: Multiphysics engineering simulation toward exascale 

    Vázquez, Mariano; Houzeaux, Guillaume; Koric, Seid; Artigues, Antoni; Aguado-Sierra, Jazmin; Arís, Ruth; Mira, Daniel; Calmet, Hadrien; Cucchietti, Fernando; Owen, Herbert; Taha, Ahmed; Burness, Evan D.; Cela, José M.; Valero Cortés, Mateo (Elsevier, 2016-02-01)
    Article
    Open Access
    Alya is a multi-physics simulation code developed at Barcelona Supercomputing Center (BSC). From its inception Alya code is designed using advanced High Performance Computing programming techniques to solve coupled problems ...
  • Alya: Multiphysics engineering simulation toward exascale 

    Vázquez, Mariano; Houzeaux, Guillaume; Koric, Seid; Artigues, Antoni; Aguado Sierra, Jazmin; Arís Sánchez, Ruth; Mira, Daniel; Calmet, Hadrien; Cucchietti, Fernando; Owen, Herbert; Taha, Ahmed; Dering Burness, Evan; Cela Espín, José M.; Valero Cortés, Mateo (Elsevier, 2016-05)
    Article
    Open Access
    Alya is a multi-physics simulation code developed at Barcelona Supercomputing Center (BSC). From its inception Alya code is designed using advanced High Performance Computing programming techniques to solve coupled problems ...
  • AMMC: advance multi-core memory controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference lecture
    Open Access
    In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...
  • An abstraction methodology for the evaluation of multi-core multi-threaded architectures 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (IEEE Computer Society Publications, 2011)
    Conference report
    Restricted access - publisher's policy
    As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ...
  • Analysis and simulation of multiplexed single-bus networks with and without buffering 

    Llaberia Griñó, José M.; Valero Cortés, Mateo; Herrada Lillo, Enrique; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 1985)
    Conference report
    Open Access
    Performance issues of a single-bus interconnection network for multiprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. ...
  • An analyzable memory controller for hard real-time CMPs 

    Paolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2010-02-05)
    Article
    Open Access
    Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ...
  • An evaluation of different DLP alternatives for the embedded media domain 

    Salamí San Juan, Esther; Corbal San Adrián, Jesús; Valero Cortés, Mateo; Espasa Sans, Roger (1999)
    Conference report
    Open Access
    The importance of media processing has produced a revolution in the design of embedded processors. In order to face the high computational and technological demands of near future media applications, new embedded processors ...
  • A new pointer-based instruction queue design and its power-performance evaluation 

    Ramírez, Marco A; Cristal Kestelman, Adrián; Veidenbaum, Alexander V; Villa, Luis; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization ...
  • An integrated vector-scalar design on an in-order ARM core 

    Stanic, Milan; Palomar Pérez, Óscar; Hayes, Timothy; Ratkovic, Ivan; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (2017-07)
    Article
    Open Access
    In the low-end mobile processor market, power, energy, and area budgets are significantly lower than in the server/desktop/laptop/high-end mobile markets. It has been shown that vector processors are a highly energy-efficient ...
  • An MPEG-4 performance study for non-SIMD, general purpose architectures 

    McKee, Sally A.; Fang, Zhen; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Conference report
    Open Access
    MPEG-4 is an important international standard with wide applicability. This paper focuses on MPEG-4's main profile, video, whose approach allows more efficiency in coding and more flexibility in managing heterogeneous media ...
  • A novel architecture for large windows processors 

    González, Isidro; Galluzzi, Marco; Veidenbaum, Alex; Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2007-11)
    External research report
    Open Access
    Several processor architectures with large instruction windows have been proposed. They improve performance by maintaining hundreds of instructions in flight to increase the level of instruction parallelism (ILP). Such ...
  • A performance characterization of high definition digital video decoding using H.264/AVC 

    Álvarez Mesa, Mauricio; Salamí San Juan, Esther; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    H.264/AVC is a new international video coding standard that provides higher coding efficiency with respect to previous standards at the expense of a higher computational complexity. The complexity is even higher when ...
  • APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation 

    Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown ...
  • Architectural support for real-time task scheduling in SMT processors 

    Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernández, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2005)
    External research report
    Open Access
    In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. ...
  • Architectural support for task dependence management with flexible software scheduling 

    Castillo, Emilio; Álvarez Martí, Lluc; Moreto Planas, Miquel; Casas, Marc; Vallejo, Enrique; Bosque, Jose L.; Beivide Palacio, Ramon; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    The growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its ...
  • Architecture for object-oriented programming model 

    Markovic, Nikola; González, Rubén; Unsal, Osman Sabri; Valero Cortés, Mateo; Cristal Kestelman, Adrián (2009)
    External research report
    Open Access
    Current mainstream architectures have ISAs that are not able to maintain all the information provided by the application programmer using a high level programming language. Typically, the information that is lost in compiling ...