Now showing items 21-27 of 27

  • Simulation methodologies for future large-scale parallel systems 

    Grass, Thomas (Universitat Politècnica de Catalunya, 2017-10-09)
    Doctoral thesis
    Open Access
    Since the early 2000s, computer systems have seen a transition from single-core to multi-core systems. While single-core systems included only one processor core on a chip, current multi-core processors include up to tens ...
  • Study and improvement of emerging applications by means of vector architectures 

    Barredo Ferreira, Adrián (Universitat Politècnica de Catalunya, 2017-07-03)
    Master thesis
    Restricted access - confidentiality agreement
  • Systematic Extraction of Code-Representative Microbenchmarks 

    Bulla, Calvin (Universitat Politècnica de Catalunya, 2017-07-11)
    Master thesis
    Restricted access - confidentiality agreement
  • Tècniques de paral·lelització del simulador Facesim 

    Vidal Ortiz, Raul (Universitat Politècnica de Catalunya, 2015-01-26)
    Bachelor thesis
    Open Access
    [CASTELLÀ] Este proyecto hace una evaluación de OmpSs como tecnología para entornos de centros de datos en busca de mejoras en el mantenimiento de aplicaciones así como su eficiencia y costes. Facesim ha sido utilizada ...
  • Towards resource-aware computing for task-based runtimes and parallel architectures 

    Chasapis, Dimitrios (Universitat Politècnica de Catalunya, 2019-04-24)
    Doctoral thesis
    Open Access
    Current large scale systems show increasing power demands, to the point that it has become a huge strain on facilities and budgets. The increasing restrictions in terms of power consumption of High Performance Computing ...
  • Transparent management of scratchpad memories in shared memory programming models 

    Álvarez Martín, Lluc (Universitat Politècnica de Catalunya, 2015-12-16)
    Doctoral thesis
    Open Access
    Cache-coherent shared memory has traditionally been the favorite memory organization for chip multiprocessors thanks to its high programmability. In this organization the cache hierarchy is in charge of moving the data and ...
  • Verification Strategy for a RISC-V Core Design 

    Jiménez Arador, Víctor (Universitat Politècnica de Catalunya, 2019-07-04)
    Bachelor thesis
    Open Access
    Covenantee:  Barcelona Supercomputing Centre
    Aquest projecte té com a finalitat la definició i l'aplicació d'una estratègia de verificació per poder comprovar el correcte funcionament i adequat respecte a l'especificació d'un nucli d'un processador basat en l'ISA ...