Now showing items 21-24 of 24

  • Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits 

    García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
    Conference report
    Open Access
    As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit ...
  • Turtle logic: Novel IC digital probabilistic design methodology 

    García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2010)
    Conference report
    Open Access
    Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and ...
  • Variability impact on on-chip memory data paths 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014)
    Conference lecture
    Open Access
    Process variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a data path. In our study, the ...
  • Variation tolerant self-adaptive clock generation architecture based on a ring oscillator 

    Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (Institute of Electrical and Electronics Engineers (IEEE), 2012)
    Conference lecture
    Open Access
    In this work we propose a self-adaptive clock based on a ring oscillator as the solution for the increasing uncertainty in the critical path delay. This increase in uncertainty forces to add more safety margins to the ...