Now showing items 21-40 of 49

  • MASkIt: soft error rate estimation for combinatorial circuits 

    Anglada Sánchez, Martí; Canal Corretger, Ramon; Aragon, Juan Luis; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation ...
  • MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment 

    Kaliorakis, Manolis; Gizopoulos, Dimitris; Canal Corretger, Ramon; González Colás, Antonio María (Association for Computing Machinery (ACM), 2017)
    Conference report
    Open Access
    Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural ...
  • Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm 

    Amat Bertran, Esteve; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2012)
    Conference report
    Open Access
    3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant ...
  • Modem gain-cell memories in advanced technologies 

    Amat Bertran, Esteve; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- ...
  • MODEST: a model for energy estimation under spatio-temporal variability 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Conference report
    Restricted access - publisher's policy
    Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental ...
  • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-12-05)
    External research report
    Restricted access - publisher's policy
    In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ...
  • On the photometric homogeneity of type IA supernovae 

    Bravo Guil, Eduardo; Domínguez, Inmaculada; Isern Vilaboy, Jordi; Canal Corretger, Ramon; Höflich, P.; Labay, Javier (1993-03)
    Article
    Open Access
    The dependence of the characteristics of the light curves of Type Ia supernovae on the ignition density of the progenitor white dwarf is studied with the aid of two models of propagation of the thermonuclear burning front: ...
  • Optimization of FinFET-based gain cells for low power sub-vt embedded drams 

    Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2018-06-01)
    Article
    Open Access
    Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ...
  • Power- and complexity-aware issue queue designs 

    Abella Ferrer, Jaume; Canal Corretger, Ramon; González Colás, Antonio María (2003-09)
    Article
    Open Access
    The improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem.
  • Power- and Performance - Aware Architectures 

    Canal Corretger, Ramon (Universitat Politècnica de Catalunya, 2004-06-14)
    Doctoral thesis
    Open Access
    The scaling of silicon technology has been ongoing for over forty years. We are on the way to commercializing devices having a minimum feature size of one-tenth of a micron. The push for miniaturization comes from the ...
  • Power-efficient spilling techniques for chip multiprocessors 

    Herrero Abellanas, Enric; González, José; Canal Corretger, Ramon (Springer Verlag, 2010)
    Conference report
    Restricted access - publisher's policy
    Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high-demand of the on-chip network and ...
  • Power/performance/thermal design-space exploration for multicore architectures 

    Monchiero, Matteo; Canal Corretger, Ramon; González Colás, Antonio María (2008-05)
    Article
    Open Access
    Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better ...
  • Process variability in sub-16nm bulk CMOS technology 

    Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon (2012-03-01)
    External research report
    Open Access
    The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.
  • REEM: failure/non-failure region estimation method for SRAM yield analysis 

    Rana, Manish; Canal Corretger, Ramon (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    The big challenge that we face today for designing resilient memories is the huge number of simulations needed to arrive at a good estimate of memory's yield. A lot of work has come up recently focusing on the reduction ...
  • Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability 

    Liang, Xiaoyao; Canal Corretger, Ramon; Wei, Gu-Yeon (2008-02)
    Article
    Open Access
    With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the ...
  • Review on suitable eDRAM configurations for next nano-metric electronics era 

    Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (2018-03)
    Article
    Open Access
    We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ...
  • Software-controlled operand-gating 

    Canal Corretger, Ramon; González Colás, Antonio María; Smith, James E. (IEEE Computer Society, 2004)
    Conference report
    Open Access
    Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method for implementing software-controlled power ...
  • SSFB: a highly-efficient and scalable simulation reduction technique for SRAM yield analysis 

    Rana, Manish; Canal Corretger, Ramon (European Interactive Digital Advertising Alliance (EDAA), 2014)
    Conference report
    Restricted access - publisher's policy
    Estimating extremely low SRAM failure-probabilities by conventional Monte Carlo (MC) approach requires hundreds-of-thousands simulations making it an impractical approach. To alleviate this problem, failure-probability ...
  • Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation 

    Rana, Manish; Canal Corretger, Ramon; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ...
  • Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation 

    Rana, Manish; Canal Corretger, Ramon; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2017-03-01)
    Article
    Open Access
    Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ...