Now showing items 21-40 of 64

    • Impact of positive bias temperature instability (PBTI) 

      Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María (2011)
      Conference report
      Restricted access - publisher's policy
      Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ...
    • INFORMER: an integrated framework for early-stage memory robustness analysis 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; González Colás, Antonio María; Rubio Sola, Jose Antonio (European Interactive Digital Advertising Alliance (EDAA), 2014)
      Conference report
      Restricted access - publisher's policy
      With the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware ...
    • iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Open Access
      Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ...
    • Lightweight protection of cryptographic hardware accelerators against differential fault analysis 

      Lasheras Mas, Ana; Canal Corretger, Ramon; Rodríguez Luna, Eva; Cassano, Luca (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      Hardware acceleration circuits for cryptographic algorithms are largely deployed in a wide range of products. The HW implementations of such algorithms often suffer from a number of vulnerabilities that expose systems to ...
    • MASkIt: soft error rate estimation for combinatorial circuits 

      Anglada Sánchez, Martí; Canal Corretger, Ramon; Aragon, Juan Luis; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Restricted access - publisher's policy
      Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation ...
    • MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment 

      Kaliorakis, Manolis; Gizopoulos, Dimitris; Canal Corretger, Ramon; González Colás, Antonio María (Association for Computing Machinery (ACM), 2017)
      Conference report
      Open Access
      Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural ...
    • Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm 

      Amat Bertran, Esteve; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2012)
      Conference report
      Open Access
      3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant ...
    • Modem gain-cell memories in advanced technologies 

      Amat Bertran, Esteve; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference report
      Open Access
      With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- ...
    • MODEST: a model for energy estimation under spatio-temporal variability 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Conference report
      Restricted access - publisher's policy
      Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental ...
    • Nanoelectronic Circuit Design 

      Canal Corretger, Ramon (Universitat Politècnica de Catalunya, 2016)
      Lecture notes
      Open Access
    • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-12-05)
      External research report
      Restricted access - publisher's policy
      In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ...
    • On the photometric homogeneity of type IA supernovae 

      Bravo Guil, Eduardo; Domínguez, Inmaculada; Isern Vilaboy, Jordi; Canal Corretger, Ramon; Höflich, P.; Labay, Javier (1993-03)
      Article
      Open Access
      The dependence of the characteristics of the light curves of Type Ia supernovae on the ignition density of the progenitor white dwarf is studied with the aid of two models of propagation of the thermonuclear burning front: ...
    • On the use of probabilistic worst-case execution time estimation for parallel applications in high performance systems 

      Fusi, Matteo; Mazzocchetti, Fabio; Farres, Albert; Kosmidis, Leonidas; Canal Corretger, Ramon; Cazorla Almeida, Francisco Javier; Abella Ferrer, Jaume (Multidisciplinary Digital Publishing Institute (MDPI), 2020-03-01)
      Article
      Open Access
      Some high performance computing (HPC) applications exhibit increasing real-time requirements, which call for effective means to predict their high execution times distribution. This is a new challenge for HPC applications ...
    • Optimization of FinFET-based gain cells for low power sub-vt embedded drams 

      Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2018-06-01)
      Article
      Open Access
      Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ...
    • Platform-agnostic steal-time measurement in a guest operating system 

      Verdú Mulà, Javier; Costa Prats, Juan José; Otero Calviño, Beatriz; Rodríguez Luna, Eva; Pajuelo González, Manuel Alejandro; Canal Corretger, Ramon (2018-10)
      External research report
      Open Access
      Steal time is a key performance metric for applications executed in a virtualized environment. Steal time measures the amount of time the processor is preempted by code outside the virtualized environment. This, in turn, ...
    • Power- and complexity-aware issue queue designs 

      Abella Ferrer, Jaume; Canal Corretger, Ramon; González Colás, Antonio María (2003-09)
      Article
      Open Access
      The improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem.
    • Power- and Performance - Aware Architectures 

      Canal Corretger, Ramon (Universitat Politècnica de Catalunya, 2004-06-14)
      Doctoral thesis
      Open Access
      The scaling of silicon technology has been ongoing for over forty years. We are on the way to commercializing devices having a minimum feature size of one-tenth of a micron. The push for miniaturization comes from the ...
    • Power-efficient spilling techniques for chip multiprocessors 

      Herrero Abellanas, Enric; González, José; Canal Corretger, Ramon (Springer Verlag, 2010)
      Conference report
      Restricted access - publisher's policy
      Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high-demand of the on-chip network and ...
    • Power/performance/thermal design-space exploration for multicore architectures 

      Monchiero, Matteo; Canal Corretger, Ramon; González Colás, Antonio María (2008-05)
      Article
      Open Access
      Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better ...
    • Predictive reliability and fault management in exascale systems: State of the art and perspectives 

      Canal Corretger, Ramon; Hernández Luz, Carles; Tornero Gavilá, Rafael; Cilardo, Alessandro; Massari, Giuseppe; Reghenzani, Federico; Fornaciari, William; Zapater Sancho, Marina; Atienza, David; Oleksiak, Ariel; Wojciech Piatek, Poznan; Abella Ferrer, Jaume (2020-09)
      Article
      Open Access
      Performance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, due ...