Ara es mostren els items 16-35 de 212

    • Aging Assessment and Design Enhancement of Randomized Cache Memories 

      Trilla, David; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-01-17)
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      Critical real-time systems require the estimation of the worst-case execution time (WCET) for scheduling purposes and resource budgeting. Measurement-based probabilistic timing analysis (MBPTA) has been shown recently as ...
    • An academic RISC-V silicon implementation based on open-source components 

      Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
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      The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...
    • An approach for detecting power peaks during testing and breaking systematic pathological behavior 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2019)
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      The verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on ...
    • An automotive case study on the limits of approximation for object detection 

      Caro Roca, Martí; Tabani, Hamid; Abella Ferrer, Jaume; Moll Echeto, Francisco de Borja; Morancho Llena, Enrique; Canal Corretger, Ramon; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Cazorla Almeida, Francisco Javier; Rubio Romano, Antonio; Fontova Muste, Pau; Fornt Mas, Jordi (2023-05)
      Article
      Accés restringit per política de l'editorial
      The accuracy of camera-based object detection (CBOD) built upon deep learning is often evaluated against the real objects in frames only. However, such simplistic evaluation ignores the fact that many unimportant objects ...
    • An energy-efficient GeMM-based convolution accelerator with on-the-fly im2col 

      Fornt Mas, Jordi; Fontova Muste, Pau; Caro Roca, Martí; Abella Ferrer, Jaume; Moll Echeto, Francisco de Borja; Altet Sanahujes, Josep; Studer, Christoph (2023-11)
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      Systolic array architectures have recently emerged as successful accelerators for deep convolutional neural network (CNN) inference. Such architectures can be used to efficiently execute general matrix–matrix multiplications ...
    • Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification 

      Espinosa, Jaime; Hernandez, Carles; Abella Ferrer, Jaume; de Andres, David; Ruiz, Juan C. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated ...
    • APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation 

      Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Text en actes de congrés
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      Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown ...
    • Applying measurement-based probabilistic timing analysis to buffer resources 

      Kosmidis, Leonidas; Vardanega, Tulio; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2013)
      Text en actes de congrés
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      The use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal ...
    • ASCOM: Affordable Sequence-aware COntention Modeling in crossbar-based MPSoCs 

      Giesen León, Jeremy Jens; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2023)
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      Multicore interference that arises when several accesses contend for the same shared hardware resources poses a challenge to the already demanding consolidated verification and validation practice. The Sequence-Aware Pairing ...
    • Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software Guidelines 

      Tabani, Hamid; Kosmidis, Leonidas; Abella Ferrer, Jaume; Cazorla, Francisco J.; Bernat, Guillem (Association for Computing Machinery (ACM), 2019-06-06)
      Comunicació de congrés
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      The complexity and size of Autonomous Driving (AD) software are comparably higher than that of software implementing other (standard) functionalities in the car. To make things worse, a big fraction of AD software is not ...
    • At-scale evaluation of weight clustering to enable energy-efficient object detection 

      Caro, Martí; Tabani, Habani; Abella Ferrer, Jaume (Elsevier, 2022)
      Article
      Accés restringit per política de l'editorial
      Accelerators implementing Deep Neural Networks (DNNs) for image-based object detection operate on large volumes of data due to fetching images and neural network parameters, especially if they need to process video streams, ...
    • AURIX TC277 Multicore Contention Model Integration for Automotive Applications 

      Mezzetti, Enrico; Barbina, Luca; Abella Ferrer, Jaume; Botta, Stefania; Cazorla, Francisco J. (IEEE, 2019-05-16)
      Comunicació de congrés
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      The ability to produce early guaranteed performance (worst-case execution time) estimates for multicores, i.e. before software from different providers gets integrated onto the same critical system, is pivotal. This helps ...
    • Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story 

      Fuentes, Francisco; Alcaide Portet, Sergi; Casanova, Raimon; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Comunicació de congrés
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      Functional and performance validation of high-performance safety-related hardware platforms require generating specific traffic patterns in the network-on-chip (NoC) to test IP components and their integration. Software-only ...
    • Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis 

      Slijepcevic, Mladen; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2017-09-28)
      Comunicació de congrés
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      Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical ...
    • Bus designs for time-probabilistic multicore processors 

      Jalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (European Interactive Digital Advertising Alliance (EDAA), 2014)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ...
    • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06-24)
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      Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...
    • Characterizing fault propagation in safety-critical processor designs 

      Espinosa, Jaime; Hernandez, Carles; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Text en actes de congrés
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      Achieving reduced time-to-market in modern electronic designs targeting safety critical applications is becoming very challenging, as these designs need to go through a certification step that introduces a non-negligible ...
    • CleanET: enabling timing validation for complex automotive systems 

      Vilardell Moreno, Sergi; Serra Mochales, Isabel; Tabani, Hamid; Abella Ferrer, Jaume; del Castillo Franquet, Joan; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020)
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      Timing validation for automotive systems occurs in late integration stages when it is hard to control how the instances of software tasks overlap in time. To make things worse, in complex software systems, like those for ...
    • Compiler directed early register release 

      Jones, Timothy M.; O’Boyle, Michael F.P.; Abella Ferrer, Jaume; González Colás, Antonio María; Ergin, Oguz (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies registers that mil only be read once and renames ...
    • Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration 

      Fernandez, Gabriel; Jalle, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2016-10-11)
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      Accés obert
      Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which ...