Browsing by Author "Moll Echeto, Francisco de Borja"
Now showing items 1-20 of 98
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A battery-less, self-sustaining RF energy harvesting circuit with TFETs for µW power applications
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessThis paper proposes a Tunnel FET (TFET) power management circuit for RF energy harvesting applications. In contrast with conventional MOSFET technologies, the improved electrical characteristics of TFETs promise a better ... -
A boolean rule-based approach for manufacturability-aware cell routing
(2014-03-01)
Article
Open AccessAn approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ... -
A comprehensive method to taxonomize mechanical energy harvesting technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Restricted access - publisher's policyTraditional industry is experiencing a worldwide development with Industry 4.0. Wireless sensor networks (WSNs) have a main role in this revolution as an essential part of data acquisition. The way in which WSNs are powered ... -
A new probabilistic design methodology of nanoscale digital circuits
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Conference report
Restricted access - publisher's policyThe continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ... -
A single event transient hardening circuit design technique based on strengthening
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyIn a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ... -
Active radiation-hardening strategy in bulk FinFETs
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Article
Open AccessIn this paper, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates ... -
All-digital self-adaptive PVTA variation aware clock generation system for DFS
(2014)
Conference report
Open AccessAn all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition ... -
All-digital simple clock synthesis through a glitch-free variable-length ring oscillator
(2014-02-01)
Article
Restricted access - publisher's policyThis brief presents a simple all-digital variable-length ring oscillator (VLRO) design that is capable of synchronously changing the output frequency while keeping a signal free of glitches or spurious oscillations at the ... -
An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
An automotive case study on the limits of approximation for object detection
(2023-05)
Article
Restricted access - publisher's policyThe accuracy of camera-based object detection (CBOD) built upon deep learning is often evaluated against the real objects in frames only. However, such simplistic evaluation ignores the fact that many unimportant objects ... -
An energy-efficient GeMM-based convolution accelerator with on-the-fly im2col
(2023-11)
Article
Open AccessSystolic array architectures have recently emerged as successful accelerators for deep convolutional neural network (CNN) inference. Such architectures can be used to efficiently execute general matrix–matrix multiplications ... -
An on-line test strategy and analysis for a 1T1R crossbar memory
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Conference report
Open AccessMemristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ... -
Analysis and modelling of parasitic substrate coupling in CMOS circuits
(1995-10)
Article
Restricted access - publisher's policyAnalysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ... -
Analysis of body bias and RTN-induced frequency shift of low voltage ring oscillators in FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Restricted access - publisher's policyElectronic circuits powered at ultra low voltages (500 mV and below) are desirable for their low energy and power consumption. However, RTN (Random Telegraph Noise)-induced threshold voltage variations become very significant ... -
Analysis of random body bias application in FDSOI cryptosystems as a countermeasure to leakage-based power analysis attacks
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Article
Open AccessThis paper analyses a novel countermeasure to Leakage Power Analysis Attacks based on the application of a random Body Bias voltage level at the beginning of the encryption process. The countermeasure effectiveness is ... -
ASIC implementation of an all-digital self-adaptive PVTA variation-aware clock generation system
(Association for Computing Machinery (ACM), 2016)
Conference report
Restricted access - publisher's policyAn all-digital self-adaptive clock generation system capable of autonomously adapt the clock frequency to compensate the effects of static spatially heterogeneous (SSHet) PVTA variations is presented. The design uses ... -
Asynchronous pulse logic cell for threshold logic and Boolean networks
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Conference report
Restricted access - publisher's policyIn this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ... -
Body bias generators for ultra low voltage circuits in FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Restricted access - publisher's policyElectronic circuits powered at ultra low voltages (300 mV and below) are desirable for their low energy and power consumption. However, the performance at such low power voltage is severely degraded. FDSOI technology, with ... -
Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture
(2012)
Conference lecture
Open Access -
Current balancing random body bias in FDSOI cryptosystems as a countermeasure to leakage power analysis attacks
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Article
Open AccessThis paper identifies vulnerabilities to recently proposed countermeasures to leakage power analysis attacks in FDSOI systems based on the application of a random body bias. The vulnerabilities are analyzed and the relative ...
