Now showing items 1-20 of 26

    • A multithreading RISC-V implementation for Lagarto Architecture 

      Mendoza Escobar, Jonnatan (Universitat Politècnica de Catalunya, 2020-04)
      Master thesis
      Open Access
      The development of computer architecture standards for many years was mainly delegated to a few groups of companies that define most of the popular Instructions Set Architectures (ISAs). While the Information Technologies ...
    • Advanced analytics through FPGA based query processing and deep reinforcement learning 

      Malazgirt, Gorker Alp (Universitat Politècnica de Catalunya, 2019-02-12)
      Doctoral thesis
      Open Access
      Today, vast streams of structured and unstructured data have been incorporated in databases, and analytical processes are applied to discover patterns, correlations, trends and other useful relationships that help to take ...
    • Affordable kilo-instruction processors 

      Pericàs Gleim, Miquel (Universitat Politècnica de Catalunya, 2008-12-09)
      Doctoral thesis
      Open Access
      Diversos motius expliquen l'estancament en el que es troba el desenvolupament del processador tradicional dissenyat per maximitzar el rendiment d'un únic fil d'execució. Per una banda, técniques agressives com la supersegmentacó ...
    • Aggressive undervolting of FPGAs : power & reliability trade-offs 

      Salami, Behzad (Universitat Politècnica de Catalunya, 2018-11-19)
      Doctoral thesis
      Open Access
      In this work, we evaluate aggressive undervolting, i.e., voltage underscaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by ...
    • Atomic dataflow model 

      Gajinov, Vladimir (Universitat Politècnica de Catalunya, 2014-11-20)
      Doctoral thesis
      Open Access
      With the recent switch in the design of general purpose processors from frequency scaling of a single processor core towards increasing the number of processor cores, parallel programming became important not only for ...
    • Beehive: an FPGA-based multiprocessor architecture 

      Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2009-09-23)
      Master thesis
      Open Access
      In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for ...
    • Circuit designs for increasing reliability and reducing energy 

      Seyedi, Azamolsadat (Universitat Politècnica de Catalunya, 2016-02-02)
      Doctoral thesis
      Open Access
      Computing technology has witnessed an inimitable progress in the last decades which is the result of CMOS technology scaling commensurate with Moore's law. Transistor feature sizes have shrunk to half at each generation, ...
    • Design and implementation of a Multimedia Extension for a RISC Processor 

      Martínez Montes, Eduardo Jonathan (Universitat Politècnica de Catalunya, 2015-07-02)
      Master thesis
      Open Access
      Design and implementation of a Multimedia Extension for a RISC Processor in a FPGA
    • Design and implementation of an out of order execution engine of floating point arithmetic operations 

      Ramírez Lazo, Cristóbal (Universitat Politècnica de Catalunya, 2016-02-04)
      Master thesis
      Open Access
      Covenantee:   Instituto Politécnico Nacional. Centro de Investigación en Computación
      In this thesis, work is undertaken towards the design in hardware description languages and implementation in FPGA of an out of order execution engine of floating point arithmetic operations. This thesis work, is part of ...
    • Design of a Load / Store Queue with Out-of-Order Execution 

      Ruíz Ramírez, Abraham Josafat (Universitat Politècnica de Catalunya, 2016-01)
      Master thesis
      Restricted access - confidentiality agreement
    • Designs for increasing reliability while reducing energy and increasing lifetime 

      Yalcin, Gulay (Universitat Politècnica de Catalunya, 2014-12-12)
      Doctoral thesis
      Open Access
      In the last decades, the computing technology experienced tremendous developments. For instance, transistors' feature size shrank to half at every two years as consistently from the first time Moore stated his law. ...
    • Enhancing the efficiency and practicality of software transactional memory on massively multithreaded systems 

      Kestor, Gökçen (Universitat Politècnica de Catalunya, 2013-03-22)
      Doctoral thesis
      Open Access
      Chip Multithreading (CMT) processors promise to deliver higher performance by running more than one stream of instructions in parallel. To exploit CMT's capabilities, programmers have to parallelize their applications, ...
    • Extending the applicability of deterministic multithreading 

      Nowack, Vesna (Universitat Politècnica de Catalunya, 2016-01-12)
      Doctoral thesis
      Open Access
      With the increased number of cores on a single processor chip, an application can achieve good performance if it splits the execution into multiple threads that run on multiple cores at the same time. To synchronize threads, ...
    • From FPGA to ASIC: A RISC-V processor experience 

      Rojas Morales, Carlos (Universitat Politècnica de Catalunya, 2019-10-25)
      Master thesis
      Open Access
      Covenantee:   Instituto Politécnico Nacional. Centro de Investigación en Computación
      This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC.
    • Hardware thread scheduling algorithms for single-ISA asymmetric CMPs 

      Markovic, Nikola (Universitat Politècnica de Catalunya, 2015-12-22)
      Doctoral thesis
      Open Access
      Through the past several decades, based on the Moore's law, the semiconductor industry was doubling the number of transistors on the single chip roughly every eighteen months. For a long time this continuous increase in ...
    • Improving heterogeneous system efficiency : architecture, scheduling, and machine learning 

      Nemirovsky, Daniel A. (Universitat Politècnica de Catalunya, 2017-10-30)
      Doctoral thesis
      Open Access
      Computer architects are beginning to embrace heterogeneous systems as an effective method to utilize increases in transistor densities for executing a diverse range of workloads under varying performance and energy ...
    • Improving the performance and energy-efficiency of virtual memory 

      Karakostas, Vasileios (Universitat Politècnica de Catalunya, 2016-04-18)
      Doctoral thesis
      Open Access
      Virtual memory improves programmer productivity, enhances process security, and increases memory utilization. However, virtual memory requires an address translation from the virtual to the physical address space on every ...
    • Low Energy DRAM Controller for Computer Systems 

      González Trejo, Alberto (Universitat Politècnica de Catalunya, 2019-07-04)
      Master thesis
      Open Access
      In this work, we leverage an open source simulation framework to evaluate different memory scheduling algorithms and we provide an architectural design of a memory controller, which is implemented in Verilog and tested on ...
    • Multicore architecture prototyping on reconfigurable devices 

      Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2016-04-15)
      Doctoral thesis
      Open Access
      In the the last decades several performance walls were hit. The memory wall and the power wall are limiting the performance scaling of digital microprocessors. Homogeneous multicores rely on thread-level parallelism, which ...
    • A multicore emulator with a profiling infrastructure for transactional memory on FPGA 

      Sönmez, Nehir (Universitat Politècnica de Catalunya, 2012-09-19)
      Doctoral thesis
      Open Access
      This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory ...