Browsing by Author "Amat Bertran, Esteve"
Now showing items 1-20 of 22
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2.4 Reliability assessments. General concepts
(Universitat Politècnica de Catalunya, 2024-10-29)
Lecture notes
Open Access -
A single event transient hardening circuit design technique based on strengthening
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyIn a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ... -
Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design
(2014)
Article
Open AccessNanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive ... -
Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches
(2013)
Conference report
Restricted access - publisher's policyScaling of device dimensions toward nano-scale regime has made it essential to innovate novel design techniques for improving the circuit robustness. This work proposes an implementation of adaptive proactive reconfiguration ... -
FinFET and III-V/Ge technology impact on 3T1D cell behavior
(2013)
Conference lecture
Open AccessIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability ... -
Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches
(2014)
Conference report
Open AccessThis work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained ... -
Impact of finfet and III-V/Ge technology on logic and memory cell behavior
(2013-11-20)
Article
Restricted access - publisher's policyIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ... -
Insights to memristive memory cell from a reliability perspective
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Conference report
Open AccessThe scaling roadmap of devices under a more than Moore scenario is resulting in the emergence of new types of devices. Among them, memristors seem to be promising candidates to be suitable for various areas of application ... -
Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm
(2012)
Conference report
Open Access3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant ... -
Modem gain-cell memories in advanced technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Open AccessWith the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- ... -
Proactive reconfiguration, a methodology for extending SRAM lifetime
(2012)
Conference lecture
Restricted access - publisher's policyThe proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique ... -
Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime
(IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
Conference lecture
Restricted access - publisher's policyProcess variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded ... -
Reliability study on technology trends beyond 20nm
(Lodz University of Technology, 2013)
Conference report
Restricted access - publisher's policyIn this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits ... -
Resistive random access memory variability and its mitigation schemes
(2017-03-01)
Article
Restricted access - publisher's policyThe need for design of new computing and storage paradigms has leaded to the emergence of new technologies and procedures. Among these technologies, emerging non-volatile memories such as RRAMs are getting intense attention ... -
SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET
(2014-04-01)
Article
Open AccessIn the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ... -
SRAM lifetime improvement by using adaptive proactive reconfiguration
(IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
Conference report
Restricted access - publisher's policyModern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design ... -
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation
(2017-03-01)
Article
Open AccessBio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ... -
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessBio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ... -
Statistical Lifetime Analysis in Memristive Crossbar
(2015)
Conference report
Open AccessEmerging devices for future memory technologies have attracted great attention recently. Memristors are one of the most favorable such devices, due to their high scalability and compatibility with CMOS fabrication process. ... -
Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
(2014-10-01)
Article
Open Access3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm ...
