Browsing by Author "Casas, Marc"
Now showing items 1-20 of 42
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A vulnerability factor for ECC-protected memory
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Open AccessFault injection studies and vulnerability analyses have been used to estimate the reliability of data structures in memory. We survey these metrics and look at their adequacy to describe the data stored in ECC-protected ... -
Active measurement of memory resource consumption
(IEEE, 2014)
Conference report
Open AccessHierarchical memory is a cornerstone of modern hardware design because it provides high memory performance and capacity at a low cost. However, the use of multiple levels of memory and complex cache management policies ... -
Active Measurement of the Impact of Network Switch Utilization on Application Performance
(IEEE, 2014)
Conference report
Open AccessInter-node networks are a key capability of High-Performance Computing (HPC) systems that differentiates them from less capable classes of machines. However, in spite of their very high performance, the increasing ... -
Approximating a Multi-Grid Solver
(IEEE, 2019-02-14)
Conference lecture
Open AccessMulti-grid methods are numerical algorithms used in parallel and distributed processing. The main idea of multigrid solvers is to speedup the convergence of an iterative method by reducing the problem to a coarser grid a ... -
Architectural support for task dependence management with flexible software scheduling
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Open AccessThe growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its ... -
Asynchronous and exact forward recovery for detected errors in iterative solvers
(2018-03-19)
Article
Open AccessCurrent trends and projections show that faults in computer systems become increasingly common. Such errors may be detected, and possibly corrected transparently, e.g. by Error Correcting Codes (ECC). For a program to be ... -
ATM: approximate task memoization in the runtime system
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Conference report
Open AccessRedundant computations appear during the execution of real programs. Multiple factors contribute to these unnecessary computations, such as repetitive inputs and patterns, calling functions with the same parameters or bad ... -
CATA: Criticality aware task acceleration for multicore processors
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessManaging criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ... -
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
(Association for Computing Machinery (ACM), 2015)
Conference report
Open AccessThe increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ... -
Design Space Exploration of Next-Generation HPC Machines
(2019)
Research report
Open AccessThe landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, ... -
Design trade-offs for emerging HPC processors based on mobile market technology
(2019-09-01)
Article
Open AccessHigh-performance computing (HPC) is at the crossroads of a potential transition toward mobile market processor technology. Unlike in prior transitions, numerous hardware vendors and integrators will have access to ... -
Evaluating scientific workflow execution on an asymmetric multicore processor
(Springer, 2018-02)
Conference lecture
Open AccessAsymmetric multicore architectures that integrate different types of cores are emerging as a potential solution for good performance and power efficiency. Although scheduling can be improved by utilizing an appropriate set ... -
Evaluation of HPC applications’ Memory Resource Consumption via Active Measurement
(IEE, 2016)
Article
Open AccessAs the number of compute cores per chip continues to rise faster than the total amount of available memory, applications will become increasingly starved for memory storage capacity and bandwidth, making the problem of ... -
Exploration of architectural parameters for future HPC systems
(Barcelona Supercomputing Center, 2019-05-07)
Conference report
Open Access -
Graph partitioning applied to DAG scheduling to reduce NUMA effects
(Association for Computing Machinery (ACM), 2018)
Conference lecture
Open AccessThe complexity of shared memory systems is becoming more relevant as the number of memory domains increases, with different access latencies and bandwidth rates depending on the proximity between the cores and the devices ... -
How can we improve energy efficiency through user-directed vectorization and task-based parallelization?
(Barcelona Supercomputing Center, 2015-05-05)
Conference report
Open AccessHeterogeneity, parallelization and vectorization are key techniques to improve the performance and energy efficiency of modern computing systems. However, programming and maintaining code for these architectures poses a ... -
Improving scalability of task-based programs
(Barcelona Supercomputing Center, 2015-05-05)
Conference report
Open AccessIn a multi-core era, parallel programming allows further performance improvements, but with an important programmability cost. We envision that the best approach to parallel programming that can exceed the programability, ... -
Intelligent adaptation of hardware knobs for improving performance and power consumption
(Institute of Electrical and Electronics Engineers (IEEE), 2021-01-01)
Article
Open AccessCurrent microprocessors include several knobs to modify the hardware behavior in order to improve performance, power, and energy under different workload demands. An impractical and time consuming offline profiling is ... -
iQ: an efficient and flexible queue-based simulation framework
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Conference report
Open AccessConventional system simulators are readily used by computer architects to design and evaluate their processor designs. These simulators provide reasonable levels of accuracy and execution detail but suffer from long ... -
Iteration-fusing conjugate gradient
(Association for Computing Machinery (ACM), 2017-06)
Conference lecture
Open AccessThis paper presents the Iteration-Fusing Conjugate Gradient (IFCG) approach which is an evolution of the Conjugate Gradient method that consists in i) letting computations from different iterations to overlap between them ...
