Browsing by Author "Jaksic, Zoran"
Now showing items 1-6 of 6
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A highly parameterizable framework for Conditional Restricted Boltzmann Machine based workloads accelerated with FPGAs and OpenCL
(Elsevier, 2020-03-01)
Article
Open AccessConditional Restricted Boltzmann Machine (CRBM) is a promising candidate for a multidimensional system modeling that can learn a probability distribution over a set of data. It is a specific type of an artificial neural ... -
Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations
(2012-12)
Article
Restricted access - publisher's policyWe explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. ... -
Considerations in using OpenCL on GPUs and FPGAs for throughput-oriented genomics workloads
(Elsevier, 2019-05)
Article
Open AccessThe recent upsurge in the available amount of health data and the advances in next-generation sequencing are setting the ground for the long-awaited precision medicine. To process this deluge of data, bioinformatics workloads ... -
Considerations in using OpenCL on GPUs and FPGAs for throughput-oriented genomics workloads
(Elsevier, 2019-05)
Article
Open AccessThe recent upsurge in the available amount of health data and the advances in next-generation sequencing are setting the ground for the long-awaited precision medicine. To process this deluge of data, bioinformatics workloads ... -
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Conference report
Restricted access - publisher's policyRecent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these ... -
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
(IEEE Computer Society Publications, 2012)
Conference report
Restricted access - publisher's policyIn this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access ...
