In this paper we develop a combinatorial method for the evaluation of yield of fault-tolerant systems-on-chip. The method assumes that defects are produced according to a model in which defects are lethal and affect given ...

Secure chips are in permanent risk of attacks. Physical attacks usually start removing part of the package and accessing the dice by different means: laser shots, electrical or electromagnetic probes, etc. Doing this ...

La tesis contribuye a los esfuerzos dirigidos a la consecución de modelaciones precisas de los fallos de tipo puente. La tecnología de los circuitos digitales considerados es la CMOS estática. En la tesis se utiliza un ...

Elliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. ...

The development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes ...

In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization ...

An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, ...

Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated ...

A technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented. The procedure is based on frequency-domain measurements performed at both end points of the ...