Now showing items 1-16 of 16

    • A module-based cell processor simulator 

      Cabarcas Jaramillo, Felipe; Rico Carro, Alejandro; Rodenas, David; Martorell Bofill, Xavier; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2006)
      Conference lecture
      Open Access
      An interesting design alternative to replication-based chip multiprocessors is to create heterogeneous chip multiprocessors composed of several different cores, with one or more of them running the operating system and ...
    • Adaptive runtime-assisted block prefetching on chip-multiprocessors 

      García Flores, Víctor; Rico Carro, Alejandro; Villavieja Prados, Carlos; Carpenter, Paul M.; Navarro, Nacho; Ramirez, Alex (2016-04-29)
      Article
      Open Access
      Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the ...
    • CellSim: a validated modular heterogeneous multiprocessor simulator 

      Cabarcas Jaramillo, Felipe; Rico Carro, Alejandro; Ródenas Picó, David; Martorell Bofill, Xavier; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (Thomson Editores Spain, 2007)
      Conference report
      Open Access
      As the number of transistors on a chip continues increasing the power consumption has become the most important constraint in processors design. Therefore, to increase performance, computer architects have decided to use ...
    • Comparing last-level cache designs for CMP architectures 

      Vega, Augusto; Rico Carro, Alejandro; Cabarcas, Felipe; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2010)
      Conference report
      Restricted access - publisher's policy
      The emergence of hardware accelerators, such as graphics processing units (GPUs), has challenged the interaction between processing elements (PEs) and main memory. In architectures like the Cell/B.E. or GPUs, the PEs ...
    • Criticality-aware dynamic task scheduling for heterogeneous systems 

      Chronaki, Kallia; Rico Carro, Alejandro; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard (Barcelona Supercomputing Center, 2015-05-05)
      Conference report
      Open Access
    • Evaluating execution time predictability of task-based programs on multi-core processors 

      Grass, Thomas Dieter; Rico Carro, Alejandro; Casas Guix, Marc; Moreto Planas, Miquel; Ramírez Bellido, Alejandro (Springer, 2015)
      Conference report
      Restricted access - publisher's policy
      Task-based programming models are becoming increasingly important, as they can reduce the synchronization costs of parallel programs on multi-cores. Instances of the same task type in task-based programs consist of the ...
    • Experiences with mobile processors for energy efficient HPC 

      Rajovic, Nikola; Rico Carro, Alejandro; Vipond, James; Gelado Fernandez, Isaac; Puzovic, Nikola; Ramírez Bellido, Alejandro (2013)
      Conference report
      Restricted access - publisher's policy
      The performance of High Performance Computing (HPC) systems is already limited by their power consumption. The majority of top HPC systems today are built from commodity server components that were designed for maximizing ...
    • Interleaving granularity on high bandwidth memory architecture for CMPs 

      Cabarcas, Felipe; Rico Carro, Alejandro; Etsion, Yoav; Ramírez Bellido, Alejandro (IEEE Computer Society Publications, 2010)
      Conference report
      Open Access
      Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip multiprocessors have increased the memory ...
    • On the simulation of large-scale architectures using multiple application abstraction levels 

      Rico Carro, Alejandro; Cabarcas, Felipe; Villavieja Prados, Carlos; Pavlovic, Milan; Vega, Augusto; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2012-01-23)
      Article
      Restricted access - publisher's policy
      Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not ...
    • Raising the level of abstraction : simulation of large chip multiprocessors running multithreaded applications 

      Rico Carro, Alejandro (Universitat Politècnica de Catalunya, 2013-10-29)
      Doctoral thesis
      Open Access
      The number of transistors on an integrated circuit keeps doubling every two years. This increasing number of transistors is used to integrate more processing cores on the same chip. However, due to power density and ILP ...
    • Sampled simulation of task-based programs 

      Grass, Thomas; Carlson, Trevor E.; Rico Carro, Alejandro; Ceballos, Germán; Ayguadé Parra, Eduard; Casas Guix, Marc; Moreto Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2019-02-01)
      Article
      Open Access
      Sampled simulation is a mature technique for reducing simulation time of single-threaded programs. Nevertheless, current sampling techniques do not take advantage of other execution models, like task-based execution, to ...
    • Task management analysis on the CellBE 

      Rico Carro, Alejandro; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2008-09)
      Conference report
      Restricted access - publisher's policy
      There is a clear industrial trend towards chip multiprocessors (CMP) as the most power efficient way of further increasing performance. Heterogeneous CMP architectures take one more step along this power efficiency trend ...
    • Task superscalar: an out-of-order task pipeline 

      Etsion, Yoav; Cabarcas, Felipe; Rico Carro, Alejandro; Ramírez Bellido, Alejandro; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (IEEE Computer Society Publications, 2010)
      Conference report
      Open Access
      We present Task Superscalar, an abstraction of instruction-level out-of-order pipeline that operates at the tasklevel. Like ILP pipelines, which uncover parallelism in a sequential instruction stream, task superscalar ...
    • Towards data-flow parallelization for adaptive mesh refinement applications 

      Sala Penadés, Kevin; Rico Carro, Alejandro; Beltran Querol, Vicenç (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      Adaptive Mesh Refinement (AMR) is a prevalent method used by distributed-memory simulation applications to adapt the accuracy of their solutions depending on the turbulent conditions in each of their domain regions. These ...
    • Trace-driven simulation of multithreaded applications 

      Rico Carro, Alejandro; Duran González, Alejandro; Cabarcas, Felipe; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2011)
      Conference report
      Restricted access - publisher's policy
      Over the past few years, computer architecture research has moved towards execution-driven simulation, due to the inability of traces to capture timing-dependent thread execution interleaving. However, trace-driven simulation ...
    • Vector architecture for HPC and ML 

      Rico Carro, Alejandro (Barcelona Supercomputing Center, 2018)
      Conference report
      Open Access