Now showing items 1-8 of 8

    • A hierarchical approach for generating regular floorplans 

      San Pedro Martín, Javier de; Cortadella, Jordi; Roca Pérez, Antoni (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Open Access
      The complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more ...
    • Adaptive clock with useful jitter 

      Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (2015-05-19)
      External research report
      Open Access
      The growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ...
    • Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems 

      Roca Pérez, Antoni; Hernández Gañán, Carlos; Lodde, Mario; Flich Cardo, José (2015-07-01)
      Article
      Open Access
      Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
    • Increasing the robustness of digital circuits with ring oscillator clocks 

      Machado, Lucas; Roca Pérez, Antoni; Cortadella, Jordi (2017)
      Conference report
      Open Access
      Technology scaling enables lower supply voltages, but also increases power density of integrated circuits. In this context, power integrity becomes a major concern in the implementation of highperformance designs. This ...
    • Reactive clocks with variability-tracking jitter 

      Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Conference report
      Open Access
      The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits ...
    • Ring oscillator clocks and margins 

      Cortadella, Jordi; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA ...
    • Robustness to voltage noise with ring oscillator clocks 

      Machado, Lucas; Roca Pérez, Antoni; Cortadella, Jordi (2019-04)
      Article
      Open Access
      Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of power delivery networks (PDNs). Lower supply voltages were made possible with technology scaling, but ...
    • Voltage noise analysis with ring oscillator clocks 

      Machado, Lucas; Roca Pérez, Antoni; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Conference report
      Open Access
      Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of Power Delivery Networks (PDNs). Ring Oscillators Clocks (ROCs) have been proposed as an alternative to ...