Browsing by Author "Gómez Fernández, Sergio"
Now showing items 1-13 of 13
-
A boolean rule-based approach for manufacturability-aware cell routing
(2014-03-01)
Article
Open AccessAn approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ... -
Characterisation of the MUSIC ASIC for large-area silicon photomultipliers for gamma-ray astronomy
(2023-01-01)
Article
Open AccessLarge-area silicon photomultipliers (SiPMs) are desired in many applications where large surfaces have to be covered. For instance, a large area SiPM has been developed by Hamamatsu Photonics in collaboration with the ... -
Design guidelines towards compact litho-friendly regular cells
(2011)
Conference report
Open Access -
FastIC: a fast integrated circuit for the readout of high performance detectors
(2022-05-01)
Article
Restricted access - publisher's policyThis work presents the 8-channel FastIC ASIC developed in CMOS 65¿nm technology suitable for the readout of positive and negative polarity sensors in high energy physics experiments, Cherenkov detectors and time-of-flight ... -
Lithography aware regular cell design based on a predictive technology model
(2010)
Conference report
Open AccessAs semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ... -
Lithography aware regular cell design based on a predictive technology model
(2010-12)
Article
Restricted access - publisher's policyAs semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ... -
Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
(2014-07-01)
Article
Open AccessA lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables ... -
Logic synthesis for manufacturability considering regularity and lithography printability
(IEEE Computer Society Publications, 2013)
Conference report
Restricted access - publisher's policyThis paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, ... -
Measurements of process variability in 40-nm regular and nonregular layouts
(2014-02-01)
Article
Restricted access - publisher's policyAs technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts ... -
New redundant logic design concept for high noise and low voltage scenarios
(2011-12)
Article
Restricted access - publisher's policyThis paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ... -
On the performance of STDMA Link Scheduling and Switched Beamforming Antennas in Wireless Mesh Networks
(Universitat Politècnica de Catalunya, 2009-09-02)
Master thesis (pre-Bologna period)
Open AccessWireless Mesh Networks (WMNs) aim to revolutionize Internet connectivity due to its high throughput, cost-e ectiveness and ease deployment by providing last mile connectivity and/or backhaul support to di erent cellular ... -
Regular cell design approach considering lithography-induced process variations
(Universitat Politècnica de Catalunya, 2014-10-17)
Doctoral thesis
Open AccessThe deployment delays for EUVL, forces IC design to continue using 193nm wavelength lithography with innovative and costly techniques in order to faithfully print sub-wavelength features and combat lithography induced ... -
Yield estimation model for lithography hotspot distortions
(Institution of Electrical Engineers, 2013-08-15)
Article
Restricted access - publisher's policyA yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield ...
