Now showing items 1-11 of 11

    • Another trip to the wall: how much will stacked DRAM benefit HPC? 

      Radulović, Milan; Živanovič, Darko; Ruiz, Daniel; De Supinski, Bronis; McKee, Sally; Radojković, Petar; Ayguadé Parra, Eduard (Association for Computing Machinery (ACM), 2015)
      Conference report
      Restricted access - publisher's policy
      First defined two decades ago, the memory wall remains a fundamental limitation to system performance. Recent innovations in 3D-stacking technology enable DRAM devices with much higher bandwidths than traditional DIMMs. ...
    • HPC benchmarking: scaling right and looking beyond the average 

      Radulović, Milan; Asifuzzaman, Kazi; Carpenter, Paul Matthew; Radojković, Petar; Ayguadé Parra, Eduard (Springer, 2018)
      Conference report
      Open Access
      Designing a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads that quantifies the ...
    • Large-memory nodes for energy efficient high-performance computing 

      Živanovič, Darko; Radulović, Milan; Llort, German; Zaragoza, David; Strassburg, Janko; Carpenter, Paul M.; Radojković, Petar; Ayguadé Parra, Eduard (Association for Computing Machinery (ACM), 2016)
      Conference report
      Open Access
      Energy consumption is by far the most important contributor to HPC cluster operational costs, and it accounts for a significant share of the total cost of ownership. Advanced energy-saving techniques in HPC components have ...
    • Main memory in HPC: do we need more, or could we live with less? 

      Živanovič, Darko; Pavlovic, Milan; Radulović, Milan; Shin, Hyunsung; Son, Jongpil; McKee, Sally A.; Carpenter, Paul M.; Radojković, Petar; Ayguadé Parra, Eduard (2017-03)
      Article
      Open Access
      An important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with ...
    • Main memory latency simulation: the missing link 

      Sánchez Verdejo, Rommel; Asifuzzaman, Kazi; Radulović, Milan; Radojković, Petar; Ayguadé Parra, Eduard; Jacob, Bruce (Association for Computing Machinery (ACM), 2018)
      Conference report
      Open Access
      The community accepted the need for a detailed simulation of main memory. Currently, the CPU simulators are usually coupled with the cycle-accurate main memory simulators. However, coupling CPU and memory simulators is not ...
    • Mainstream vs. emerging HPC: metrics, trade-offs and lessons learned 

      Radulović, Milan; Asifuzzaman, Kazi; Živanovič, Darko; Rajovic, Nikola; Colin de Verdiére, Guillaume; Pleiter, Dirk; Marazakis, Manolis; Kallimanis, Nikolaos; Carpenter, Paul Matthew; Radojković, Petar; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference report
      Open Access
      Various servers with different characteristics and architectures are hitting the market, and their evaluation and comparison in terms of HPC features is complex and multidimensional. In this paper, we share our experience ...
    • Memory bandwidth and latency in HPC: system requirements and performance impact 

      Radulović, Milan (Universitat Politècnica de Catalunya, 2019-05-07)
      Doctoral thesis
      Open Access
      A major contributor to the deployment and operational costs of a large-scale high-performance computing (HPC) clusters is the memory system. In terms of system performance it is one of the most critical aspects of the ...
    • Multilevel simulation-based co-design of next generation HPC microprocessors 

      Zaourar, Lilia; Benazouz, Mohamed; Mouhagir, Ayoub; Jebali, Fatma; Sassolas, Tanguy; Weill, Jean Christophe; Radulović, Milan; Martínez Palau, Francesc; Armejach Sanosa, Adrià; Casas Guix, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation ...
    • Performance impact of a slower main memory: a case study of STT-MRAM in HPC 

      Asifuzzaman, Kazi; Pavlovic, Milan; Radulović, Milan; Zaragoza, David; Kwon, Ohseong; Ryoo, Kyung-Chang; Radojković, Petar (ACM, 2016-10)
      Conference lecture
      Open Access
      In high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) --- byte-addressable, ...
    • Performance impact of a slower main memory: a case study of STT-MRAM in HPC 

      Asifuzzaman, Kazi; Pavlovic, Milan; Radulović, Milan; Zaragoza, David; Kwon, Ohseong; Ryoo, Kyung-Chang; Radojković, Petar (Barcelona Supercomputing Center, 2017-05-04)
      Conference report
      Open Access
      Memory systems are major contributors to the deployment and operational costs of large-scale HPC clusters [1][2][3], as well as one of the most important design parameters that significantly affect system performance. In ...
    • PROFET: modeling system performance and energy without simulating the CPU 

      Radulović, Milan; Sánchez-Verdejo, Rommel; Carpenter, Paul Matthew; Radojković, Petar; Jacob, Bruce; Ayguadé Parra, Eduard (2019-06)
      Article
      Open Access
      The approaching end of DRAM scaling and expansion of emerging memory technologies is motivating a lot of research in future memory systems. Novel memory systems are typically explored by hardware simulators that are slow ...