Now showing items 1-3 of 3

    • A two level neural approach combining off-chip prediction with adaptive prefetch filtering 

      Jamet, Alexandre Valentin; Vavouliotis, Georgios; Jiménez, Daniel A.; Álvarez Martí, Lluc; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2024)
      Conference report
      Open Access
      To alleviate the performance and energy overheads of contemporary applications with large data footprints, we propose the Two Level Perceptron (TLP) predictor, a neural mechanism that effectively combines predicting whether ...
    • Characterizing the impact of last-level cache replacement policies on big-data workloads 

      Jamet, Alexandre Valentin; Álvarez Martí, Lluc; Jiménez, Daniel A.; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The vast disparity between Last Level Cache (LLC) and memory latencies has motivated the need for efficient cache management policies. The computer architecture literature abounds with work on LLC replacement policy. ...
    • Practically tackling memory bottlenecks of graph-processing workloads 

      Jamet, Alexandre Valentin; Vavouliotis, Georgios; Jiménez, Daniel A.; Álvarez Martí, Lluc; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2024)
      Conference report
      Open Access
      Graph-processing workloads have become widespread due to their relevance on a wide range of application domains such as network analysis, path- planning, bioinformatics, and machine learning. Graph-processing workloads ...