Exploració per autor "Lupon Navazo, Marc"

Ara es mostren els items 1-8 de 8

    • A Dynamically Adaptable Hardware Transactional Memory 

      Lupon Navazo, Marc; Magklis, Grigorios; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
      Text en actes de congrés
      Accés obert
      Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-place in memory and resolve conflicts ...

    • A selective logging mechanism for hardware transactional memory systems 

      Lupon Navazo, Marc; Magklis, Grigorios; González Colás, Antonio María (2011-09-19)
      Report de recerca
      Accés obert
      Log-based Hardware Transactional Memory (HTM) systems offer an elegant solution to handle speculative data that overflow transactional L1 caches. By keeping the pre-transactional values on a software-resident log, speculative ...

    • Adaptive clock with useful jitter 

      Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (2015-05-19)
      Report de recerca
      Accés obert
      The growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ...

    • Architectural support for high-performing hardware transactional memory systems 

      Lupon Navazo, Marc (Universitat Politècnica de Catalunya, 2011-12-23)
      Tesi
      Accés obert
      Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes ...

    • FASTM: a log-based hardware transactional memory with fast abort recovery 

      Lupon Navazo, Marc; Magklis, Grigorios; González Colás, Antonio María (IEEE Computer Society, 2009)
      Text en actes de congrés
      Accés obert
      Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current HTM systems use either eager or lazy version ...

    • Reactive clocks with variability-tracking jitter 

      Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Text en actes de congrés
      Accés obert
      The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits ...

    • Ring oscillator clocks and margins 

      Cortadella, Jordi; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA ...

    • Safe and efficient supervised memory systems 

      Bobba, J.; Lupon Navazo, Marc; Hill, M.D; Wood, D. A. (2011)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Supervised Memory systems use out-of-band metabits to control and monitor accesses to normal data memory for such purposes as transactional memory and memory typestate trackers. Previous proposals demonstrate the value ...