Exploració per autor "Viñals Yufera, Víctor"
Ara es mostren els items 1-8 de 8
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Block disabling characterization and improvements in CMPs operating at ultra-low voltages
Ferrerón, Alexandra; Suárez Gracia, Darío; Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertPower density has become the limiting factor in technology scaling as power budget restricts the amount of hardware that can be active at the same time. Reducing supply voltage to ultra-low voltage ranges close to the ... -
Delaying physical register allocation trought virtual-physical registers
Monreal Arnal, Teresa; González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertRegister file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This ... -
Filtering directory lookups in CMPs
Bosque, Ana; Viñals Yufera, Víctor; Ibáñez, Pablo; Llaberia Griñó, José M. (2010)
Text en actes de congrés
Accés obertCoherence protocols consume an important fraction of power to determine which coherence action should take place. In this paper we focus on CMPs with a shared cache and a directory-based coherence protocol implemented as ... -
Hardware schemes for early register release
Monreal Arnal, Teresa; Viñals Yufera, Víctor; González Colás, Antonio María; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertRegister files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the ... -
Late allocation and early release of physical registers
Monreal Arnal, Teresa; Viñals Yufera, Víctor; González González, José; González Colás, Antonio María; Valero Cortés, Mateo (2004-10)
Article
Accés obertThe register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the ... -
Light NUCA: a proposal for bridging the inter-cache latency gap
Suárez, Dario; Monreal Arnal, Teresa; Vallejo, Fernando; Beivide Palacio, Julio Ramón; Viñals Yufera, Víctor (IEEE Computer Society, 2009)
Comunicació de congrés
Accés obertTo deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). ... -
Microarchitectural support for speculative register renaming
Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertThis paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission of physical register allocation along with ... -
Selection of the register file size and the resource policy on SMT processors
Alastruey, Jesús; Monreal Arnal, Teresa; Cazorla Almeida, Francisco Javier; Viñals Yufera, Víctor; Valero Cortés, Mateo (IEEE Computer Society, 2008)
Comunicació de congrés
Accés obertThe performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared resource. In this paper we analyze the effect ...