Ara es mostren els items 1-20 de 77

  • A case study of hybrid dataflow and shared-memory programming models: Dependency-based parallel game engine 

    Gajinov, Vladimir; Eric, Igor; Stojanovic, Saa; Milutinovic, Veljko; Unsal, Osman Sabri; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    Recently proposed hybrid dataflow and shared memory programming models combine these two underlying models in order to support a wider range of problems naturally. The effectiveness of such hybrid models for parallel ...
  • Advanced pattern based memory controller for FPGA based HPC applications 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ...
  • A fully parameterizable low power design of vector fused multiply-add using active clock-gating techniques 

    Ratkovic, Ivan; Palomar, Oscar; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2016)
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    The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market ...
  • A general guide to applying machine learning to computer architecture 

    Nemirovsky, Daniel; Arkose, Tugberk; Markovic, Nikola; Nemirovsky, Mario; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2018)
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    The resurgence of machine learning since the late 1990s has been enabled by significant advances in computing performance and the growth of big data. The ability of these algorithms to detect complex patterns in data which ...
  • AMMC: advance multi-core memory controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...
  • An integrated vector-scalar design on an in-order ARM core 

    Stanic, Milan; Palomar Pérez, Óscar; Hayes, Timothy; Ratkovic, Ivan; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (2017-07)
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    In the low-end mobile processor market, power, energy, and area budgets are significantly lower than in the server/desktop/laptop/high-end mobile markets. It has been shown that vector processors are a highly energy-efficient ...
  • Architecture for object-oriented programming model 

    Markovic, Nikola; González, Rubén; Unsal, Osman Sabri; Valero Cortés, Mateo; Cristal Kestelman, Adrián (2009)
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    Current mainstream architectures have ISAs that are not able to maintain all the information provided by the application programmer using a high level programming language. Typically, the information that is lost in compiling ...
  • A runtime heuristic to selectively replicate tasks for application-specific reliability targets 

    Subasi, Omer; Yalcin, Gulay; Zyulkyarov, Ferad; Unsal, Osman Sabri; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    In this paper we propose a runtime-based selective task replication technique for task-parallel high performance computing applications. Our selective task replication technique is automatic and does not require ...
  • Atomic quake: using transactional memory in an interactive mulitplayer game Server 

    Zyulkyarov, Ferad; Gajinov, Vladimir; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Harris, Tim; Valero Cortés, Mateo (2009)
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    Transactional Memory (TM) is being studied widely as a new technique for synchronizing concurrent accesses to shared memory data structures for use in multi-core systems. Much of the initial work on TM has been evaluated ...
  • Circuit design of a dual-versioning L1 data cache for optimistic concurrency 

    Seyedi, Azam; Armejach, Adrià; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Hur, Ibrahim; Valero Cortés, Mateo (2011)
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    This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell ...
  • Circuit design of a novel adaptable and reliable L1 data cache 

    Seyedi, Azam; Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián (2013)
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    This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest reliability. ...
  • Clock gate on abort: Towards energy-efficient hardware transactional memory 

    Sanyal, Sutirtha; Roy, Sourav; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2009)
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    Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a ...
  • Commit on overflow 

    Stipic, Srdjan; Armejach, Adrià; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2014)
    Report de recerca
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    Current commercial CPUs have hardware support for speculative lock elision (SLE). SLE tries to elide the lock by speculatively executing lock protected critical section. If the speculation fails, SLE acquires the lock and ...
  • CRC-based memory reliability for task-parallel HPC applications 

    Subasi, Omer; Unsal, Osman Sabri; Labarta Mancho, Jesús José; Yalcin, Gulay; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Memory reliability will be one of the major concerns for future HPC and Exascale systems. This concern is mostly attributed to the expected massive increase in memory capacity and the number of memory devices in Exascale ...
  • DaSH: a benchmark suite for hybrid dataflow and shared memory programming models 

    Gajinov, Vladimir; Stipic, Srdjan; Eric, Igor; Unsal, Osman Sabri; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (2015-06-01)
    Article
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    The current trend in development of parallel programming models is to combine different well established models into a single programming, model in order to support efficient implementation of a wide range of real world ...
  • DaSH: a benchmark suite for hybrid dataflow and shared memory programming models: with comparative evaluation of three hybrid dataflow models 

    Gajinov, Vladimir; Stipic, Srdjan; Eric, Igor; Unsal, Osman Sabri; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (Association for Computing Machinery (ACM), 2014)
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    The current trend in development of parallel programming models is to combine different well established models into a single programming model in order to support efficient implementation of a wide range of real world ...
  • Designing and modelling selective replication for fault-tolerant HPC applications 

    Subasi, Omer; Yalcin, Gulay; Zyulkyarov, Ferad; Unsal, Osman Sabri; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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    Fail-stop errors and Silent Data Corruptions (SDCs) are the most common failure modes for High Performance Computing (HPC) applications. There are studies that address fail-stop errors and studies that address SDCs. However ...
  • Determinism at standard-library level in TM-based applications 

    Smiljkovic, Vesna; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2017-02-01)
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    Deterministic execution of a multi-threaded application guarantees that threads access shared memory in the same order and the application gives the same output whenever it runs with the same input parameters. Determinism ...
  • DeTrans: Deterministic and parallel execution of transactions 

    Smiljkovic, Vesna; Stipic, Srdjan; Fetzer, Christof; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    Deterministic execution of a multithreaded application guarantees the same output as long as the application runs with the same input parameters. Determinism helps a programmer to test and debug an application and to provide ...
  • DLP acceleration on general purpose cores 

    Duric, Milovan; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Barcelona Supercomputing Center, 2015-05-05)
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    High-performance and power-efficient multimedia computing drives the design of modern and increasingly utilized mobile devices. State-of-the-art low power processors already utilize chip multiprocessors (CMP) that add ...