Now showing items 1-20 of 69

  • A cache design for probabilistically analysable real-time systems 

    Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2013)
    Conference report
    Restricted access - publisher's policy
    Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. ...
  • Achieving timing composability with measurement-based probabilistic timing analysis 

    Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (2013)
    Conference report
    Restricted access - publisher's policy
    Probabilistic Timing Analysis (PTA) allows complex hardware acceleration features, which defeat classic timing analysis, to be used in hard real-time systems. PTA can do that because it drastically reduces intrinsic ...
  • A confidence assessment of WCET estimates for software time randomized caches 

    Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Obtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ...
  • An analyzable memory controller for hard real-time CMPs 

    Paolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2010-02-05)
    Article
    Open Access
    Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ...
  • Applying measurement-based probabilistic timing analysis to buffer resources 

    Kosmidis, Leonidas; Vardanega, Tulio; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2013)
    Conference report
    Open Access
    The use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal ...
  • Architectural support for real-time task scheduling in SMT processors 

    Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernández, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2005)
    External research report
    Open Access
    In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. ...
  • Bus designs for time-probabilistic multicore processors 

    Jalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (European Interactive Digital Advertising Alliance (EDAA), 2014)
    Conference report
    Restricted access - publisher's policy
    Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ...
  • Characterizing the resource-sharing levels of the UltraSparc T2 processor 

    Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2009)
    Conference report
    Restricted access - publisher's policy
    Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ...
  • Containing timing-related certification cost in automotive systems deploying complex hardware 

    Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Farrall, Glenn; Wartel, Franck; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
    Conference report
    Restricted access - publisher's policy
    Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ...
  • Contention-aware performance monitoring counter support for real-time MPSoCs 

    Jalle Ibarra, Javier; Fernández, Mikel; Abella, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference lecture
    Open Access
    Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ...
  • Contention in multicore hardware shared resources: Understanding of the state of the art 

    Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones, Eduardo; Rochange, Christine; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
    Conference report
    Open Access
    The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ...
  • Data bus slicing for contention-free multicore real-time memory systems 

    Jalle Ibarra, Javier; Quiñones, Eduardo; Abella, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Memory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ...
  • Dcache Warn: an I-fetch policy to increase SMT efficiency 

    Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Garcia, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    Simultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, ...
  • Deconstructing bus access control policies for real-time multicores 

    Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ...
  • DReAM: An approach to estimate per-Task DRAM energy in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2016-12)
    Article
    Open Access
    Accurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ...
  • DReAM: Per-task DRAM energy metering in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Springer, 2014)
    Conference report
    Open Access
    Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ...
  • DTM: degraded test mode for fault-aware probabilistic timing analysis 

    Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    Existing timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ...
  • Dynamically controlled resource allocation in SMT processors 

    Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Prieto, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    SMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for ...
  • Enabling SMT for real-time embedded systems 

    Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    In order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ...
  • Evolutionary system for prediction and optimization of hardware architecture performance 

    Castillo, Pedro Angel; Merelo, Juan Julián; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally (2008-06)
    Conference report
    Open Access
    The design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ...