Exploració per autor "Pericàs Gleim, Miquel"

Ara es mostren els items 1-8 de 8

    • A decoupled KILO-instruction processor 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
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      Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ...

    • A flexible heterogeneous multi-core architecture 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
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      Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this ...

    • A template system for the efficient compilation of domain abstractions onto reconfigurable computers 

      Shafiq, Muhammad; Pericàs Gleim, Miquel; Ayguadé Parra, Eduard (2011)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Past research has addressed the issue of using FPGAs as accelerators for HPC systems. However, writing low level code for an efficient, portable and scalable architecture altogether has been always a ...

    • A two level load/store queue based on execution locality 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Veidenbaum, Alexander V; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Text en actes de congrés
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      Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ...

    • Affordable kilo-instruction processors 

      Pericàs Gleim, Miquel (Universitat Politècnica de Catalunya, 2008-12-09)
      Tesi
      Accés obert
      Diversos motius expliquen l'estancament en el que es troba el desenvolupament del processador tradicional dissenyat per maximitzar el rendiment d'un únic fil d'execució. Per una banda, técniques agressives com la supersegmentacó ...

    • Chained in-order/out-of-order doublecore architecture 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; González García, Rubén; Jiménez González, Daniel; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, by increasing the size of microprocessor ...

    • LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing 

      Cristal, Adrian; Unsal, Osman S.; Martorell, Xavier; Carpenter, Paul Matthew; de la Cruz, Raul; Bautista Gomez, Leonardo; Jimenez, Daniel; Alvarez, Carlos; Salami, Behzad; Madonar, Sergi; Pericàs Gleim, Miquel; Trancoso, Pedro; vor dem Berge, Micha; Billung-Meyer, Gunnar; Krupop, Stefan; Christmann, Wolfgang; Klawonn, Frank; Mihklafi, Amani; Becker, Tobias; Gaydadjiev, Georgi; Salomonsson, Hans; Dubhashi, Devdatt; Port, Oron; Hadar, Elad; Etsion, Yoav; Fetzer, Christof; Hagemeyer, Jens; Jungeblut, Thorsten; Kucza, Nils; Kaiser, Martin; Porrmann, Mario; Pasin, Marcelo; Schiavoni, Valerio; Rocha, Isabelly; Göttel, Christian; Felber, Pascal (ACM, 2018-07-15)
      Comunicació de congrés
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      LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of ...

    • Performance and power evaluation of clustered VLIW processors with wide functional units 

      Pericàs Gleim, Miquel; Ayguadé Parra, Eduard; Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Valero Cortés, Mateo (2004-11)
      Article
      Accés restringit per política de l'editorial
      Architectural resources and program recurrences are themain limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops. To increase the number of operations per second, current designs use high ...