Ara es mostren els items 1-20 de 44

  • A cost-effective clustered architecture 

    Canal Corretger, Ramon; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1999)
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    In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute ...
  • A detailed methodology to compute soft error rates in advanced technologies 

    Riera Villanueva, Marc; Canal Corretger, Ramon; Abella, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the ...
  • An energy-efficient and scalable eDRAM-based register file architecture for GPGPU 

    Jing, Naifeng; Shen, Yao; Lu, Yao; Ganapathy, Shrikanth; Mao, Zhigang; Guo, Minyi; Canal Corretger, Ramon; Liang, Xiaoyao (ACM, 2013)
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    The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for ...
  • An hybrid eDRAM/SRAM macrocell to implement first-level data caches 

    Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Lorente, Vicente; Canal Corretger, Ramon; López, Pedro; Duato, José (Association for Computing Machinery (ACM), 2009)
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    SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are ...
  • A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio (IEEE Computer Society Publications, 2012)
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    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition ...
  • Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
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    With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ...
  • Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes 

    Lorente, Vicente; Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Canal Corretger, Ramon; López, Pedro; Duato, José (2013)
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    Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors ...
  • Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations 

    Jaksic, Zoran; Canal Corretger, Ramon (2012-12)
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    We explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. ...
  • Cross-layer system reliability assessment framework for hardware faults 

    Vallero, Alessandro; Savino, Alessandro; Politano, Gianfranco; Di Carlo, Stefano; Chatzidimitriou, Athanansios; Tselonis, Sotiris; Kaliorakis, Manolis; Gizipoulos, Dimitris; Riera Villanueva, Marc; Canal Corretger, Ramon; González Colás, Antonio María; Kooli, Maha; Bosio, Alberto; Di Natale, Giorgio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction ...
  • DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy 

    Jaksic, Zoran; Canal Corretger, Ramon (European Interactive Digital Advertising Alliance (EDAA), 2014)
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    Recent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these ...
  • Dynamic cluster assignment mechanisms 

    Canal Corretger, Ramon; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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    Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster microarchitecture with a naive code partitioning ...
  • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-04-15)
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    In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.
  • Effectiveness of hybrid recovery techniques on parametric failures 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Modern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V ddmin. On-chip memories like caches ...
  • Elastic cooperative caching: an autonomus dynamically adaptive memory hierarchy for chip multiprocessors 

    Herrero Abellanas, Enric; González, José; Canal Corretger, Ramon (Association for Computing Machinery (ACM), 2010)
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    Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of applications with very different memory needs, ...
  • Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs 

    Jaksic, Zoran; Canal Corretger, Ramon (IEEE Computer Society Publications, 2012)
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    In this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access ...
  • FinFET and III-V/Ge technology impact on 3T1D cell behavior 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; Almudever, Carmen G.; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013)
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    In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability ...
  • Impact of finfet and III-V/Ge technology on logic and memory cell behavior 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013-11-20)
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    In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ...
  • Impact of positive bias temperature instability (PBTI) 

    Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María (2011)
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    Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ...
  • INFORMER: an integrated framework for early-stage memory robustness analysis 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; González Colás, Antonio María; Rubio Sola, Jose Antonio (European Interactive Digital Advertising Alliance (EDAA), 2014)
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    With the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware ...
  • iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ...