Exploració per altres contribucions "Moll Echeto, Francisco de Borja"
Ara es mostren els items 1-20 de 50
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A Vector processing unit implementation for RISC-V vector extension: Functional verification and assertions on submodules
(Universitat Politècnica de Catalunya, 2020-09)
Projecte Final de Màster Oficial
Accés obertPower dissipation and Energy consumption of digital circuits has emerged as an important design parameter in the evaluation of microelectronic circuits. This has led electronic architects to value Parallel Architectures ... -
Actualització de pràctiques docents de comunicació Ethernet amb la Zedboard de Xilinx
(Universitat Politècnica de Catalunya, 2016)
Projecte/Treball Final de Carrera
Accés obertOver the last few years the IoT has jumped from the theory to the things we use every day, so the easy development of embedded products is a goal to accomplish. The Zedboard is an integrated board for embedded developments ... -
Analysis of clock tree implementation on ASIC block QoR
(Universitat Politècnica de Catalunya, 2017-10)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: eSiliconThe scope of this project is to develop a base methodology for clock tree synthesis that can improve the base results regarding the clock structure. The analysis of results will be done with a Quality of Results sets of ... -
Approximate arithmetic units under voltage under-scaling
(Universitat Politècnica de Catalunya, 2021-01-28)
Projecte Final de Màster Oficial
Accés obertIncreasingly power hungry processors and the identification of error tolerant applications have made approximate computing techniques one of the researching scopes of the present. The main objective of this work is to study ... -
Body bias generator design for ultra-low voltage applications in FDSOI technology
(Universitat Politècnica de Catalunya, 2019-10-14)
Projecte Final de Màster Oficial
Accés obertThis thesis presents the derivation and validation processes of analytical models describing the dynamic and steady-state behaviors of CC-CP switched capacitor converters. The effects of FDSOI components in the implementation ... -
Comparativa d'implementació hardware vs software en un sistema de processat d'imatge per a detecció de cares
(Universitat Politècnica de Catalunya, 2016-06)
Treball Final de Grau
Accés obertIn this project two implementations of a face detection system, one of them based on hardware and the other on software, have been developed. The main goal is to compare both implementations and determine the advantages ... -
Construcción de celdas regulares FDSOI 28nm utilizando herramientas automáticas
(Universitat Politècnica de Catalunya, 2015-12-17)
Projecte/Treball Final de Carrera
Accés restringit per acord de confidencialitat -
Convolutional neural networks for efficient object detection on ultra low-power platforms
(Universitat Politècnica de Catalunya, 2017-10)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Università di BolognaAt the University of Bologna, the Microelectronics Research Group has been working on smart data analytics on ultra-low-power sensors for the past few years. This smart analysis is in many cases based on convolutional ... -
Desenvolupament d'un dispositiu wearable per a mesurar patrons de respiració
(Universitat Politècnica de Catalunya, 2017-01)
Treball Final de Grau
Accés restringit per acord de confidencialitat -
Design and implementation of a smartcard reader for testing proposes
(Universitat Politècnica de Catalunya, 2016-10)
Projecte Final de Màster Oficial
Accés restringit per acord de confidencialitat -
Design and implementation of a traffic injector for a bus-based space multicore
(Universitat Politècnica de Catalunya, 2021-01-26)
Projecte Final de Màster Oficial
Accés obertReal-time multiprocessor systems have particular needs related to their design, verification, and validation. In particular, they have stringent requirements to prove that they will correctly perform their functionalities, ... -
Design and implementation of an UDP/IP Ethernet hardware protocol stack for FPGA based Systems
(Universitat Politècnica de Catalunya, 2019-01-17)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Universitat de Barcelona. Institut de Ciències del CosmosThe main objective of the thesis has been the design and implementation of a complete UDP/IP Ethernet stack that allow us the connection and use of networks by any FPGA device. The stack has been designed around Ethernet, ... -
Design for Testability methodologies applied to a RISC-Vprocessor
(Universitat Politècnica de Catalunya, 2021-01-29)
Projecte Final de Màster Oficial
Accés obertThe decrease in the size of transistors and technology nodes has made manufacturing processes increasingly difficult and unreliable, Design for Test techniques provide measures to thoroughly test the manufactured device ... -
Design of a Charge Pump-Based Body Bias Generator for FDSOI Circuits
(Universitat Politècnica de Catalunya, 2018-02)
Projecte Final de Màster Oficial
Accés obertElectronics circuits powered at near-threshold voltages (ultra-low voltage designs) are desirable for their low power consumption. However, the performance at such voltage supply is degraded. The application of forward ... -
Design of a clock and data recovery circuit in FDSOI technology for high speed serial links
(Universitat Politècnica de Catalunya, 2021-03)
Projecte Final de Màster Oficial
Accés obertThe purpose of this thesis is to design an 8 Gbps clock and data recovery circuit intended to work in the receiver of a high-speed Serializer-Deserializer interface (SerDes). The proposed architecture is based on a ... -
Design of a Computer Vision system based on the Zynq platform
(Universitat Politècnica de Catalunya, 2019-09)
Projecte Final de Màster Oficial
Accés restringit per acord de confidencialitat -
Design of a diversity enforcement module for safety critical processing systems
(Universitat Politècnica de Catalunya, 2022-07-02)
Projecte Final de Màster Oficial
Accés obertSafety-critical systems must adhere to specific functional safety standards describing the development process for those systems. One key requirement is the ability to avoid a single fault from causing a system failure, ... -
Design of an ammeter for the test of printed circuits
(Universitat Politècnica de Catalunya, 2019-01)
Treball Final de Grau
Accés obertDesign this ammeter from a current sensor. Developing around it a system capable of communicating easily with the user. -
Design of an AXI-SDRAM interface IP in a RISC-V processor
(Universitat Politècnica de Catalunya, 2020-05)
Projecte Final de Màster Oficial
Accés obertPreDRAC is a RISC-V based SoC developed with the collaboration of the BSC, CIC-IPN, IMB-CNM (CSIC) and UPC. On its first version, sent to fabricate on May 2019, it used a custom interface to access main memory through an ... -
Design of an electrical nerve stimulator using wireless power transmission through NFC
(Universitat Politècnica de Catalunya, 2018-02-05)
Projecte Final de Màster Oficial
Accés obertElectrical stimulation has been proved to be an effective method to speed up the recovery process of a peripheral nerve that has been badly injured. In this work it is designed the circuitry for a hypothetical implanted ...
