Now showing items 1-20 of 58

  • A battery-less, self-sustaining RF energy harvesting circuit with TFETs for µW power applications 

    Nunes Cavalheiro, David Manuel; Moll Echeto, Francisco de Borja; Valtchev, Stanimir (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    This paper proposes a Tunnel FET (TFET) power management circuit for RF energy harvesting applications. In contrast with conventional MOSFET technologies, the improved electrical characteristics of TFETs promise a better ...
  • A boolean rule-based approach for manufacturability-aware cell routing 

    Cortadella Fortuny, Jordi; Petit Silvestre, Jordi; Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2014-03-01)
    Article
    Open Access
    An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ...
  • All-digital self-adaptive PVTA variation aware clock generation system for DFS 

    Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (2014)
    Conference report
    Open Access
    An all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition ...
  • All-digital simple clock synthesis through a glitch-free variable-length ring oscillator 

    Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2014-02-01)
    Article
    Restricted access - publisher's policy
    This brief presents a simple all-digital variable-length ring oscillator (VLRO) design that is capable of synchronously changing the output frequency while keeping a signal free of glitches or spurious oscillations at the ...
  • Analysis and modelling of parasitic substrate coupling in CMOS circuits 

    Aragonès Cervera, Xavier; Moll Echeto, Francisco de Borja; Roca Adrover, Miquel; Rubio Sola, Jose Antonio (1995-10)
    Article
    Restricted access - publisher's policy
    Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ...
  • A new probabilistic design methodology of nanoscale digital circuits 

    García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Conference report
    Restricted access - publisher's policy
    The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ...
  • An on-line test strategy and analysis for a 1T1R crossbar memory 

    Escudero, Manel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference report
    Open Access
    Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ...
  • ASIC implementation of an all-digital self-adaptive PVTA variation-aware clock generation system 

    Pérez-Puigdemont, Jordi; Moll Echeto, Francisco de Borja (Association for Computing Machinery (ACM), 2016)
    Conference report
    Restricted access - publisher's policy
    An all-digital self-adaptive clock generation system capable of autonomously adapt the clock frequency to compensate the effects of static spatially heterogeneous (SSHet) PVTA variations is presented. The design uses ...
  • A single event transient hardening circuit design technique based on strengthening 

    Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ...
  • Asynchronous pulse logic cell for threshold logic and Boolean networks 

    Lambie, J; Moll Echeto, Francisco de Borja; González Jiménez, José Luis; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Restricted access - publisher's policy
    In this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ...
  • Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture 

    Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (2012)
    Conference lecture
    Open Access
  • Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches 

    Pouyan, Peyman; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
    Conference report
    Restricted access - publisher's policy
    Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design techniques for improving the circuit robustness. This work proposes an implementation of adaptive proactive reconfiguration ...
  • Design guidelines towards compact litho-friendly regular cells 

    Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Elhoj, Martin; Schlinker, Guilherme; Woolaway, Nigel (2011)
    Conference report
    Open Access
  • Design of complex circuits using the via-configurable transistor array regular layout fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
    Conference report
    Restricted access - publisher's policy
    Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...
  • Diseño de circuitos y sistemas integrados 

    Rubio, Antonio; Altet Sanahujes, Josep; Aragonès Cervera, Xavier; González Jiménez, José Luis; Mateo Peña, Diego; Moll Echeto, Francisco de Borja (Edicions UPC, 2003)
    Book
    Restricted access to UB, UAB, UPC, UPF, UdG, UdL, URV, UOC, BC, UVic, UJI, URL, UIC users
    La tecnología de circuitos integrados, basada principalmente en la miniaturización de los circuitos ha evolucionado intensamente en los últimos tiempos. El objetivo de esta obra es dar a conocer esta evolución reciente y ...
  • Energy macro-model for on chip interconnection buses 

    Mendoza Vázquez, Raymundo; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Figueras, Joan (2006-06)
    External research report
    Open Access
    This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. ...
  • Error probability in synchronous digital circuits due to power supply noise 

    Martorell Cid, Ferran; Pons Solé, Marc; Rubio, Antonio; Moll Echeto, Francisco de Borja (2007-09)
    Conference report
    Open Access
    This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered ...
  • Error probability in synchronous digital circuits due to power supply noise 

    Martorell Cid, Ferran; Pons, M; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja (???, 2007)
    Conference report
    Open Access
    This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered ...
  • Experience on material implication computing with an electromechanical memristor emulator 

    Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Escudero López, Manuel; Zuin, Stefano; Vourkas, Ioannis; Sirakoulis, Georgios (IEEE Press, 2016)
    Conference report
    Open Access
    Memristors are being considered as a promising emerging device able to introduce new paradigms in both data storage and computing. In this paper the authors introduce the concept of a quasi-ideal experimental device that ...
  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 

    González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
    Conference lecture
    Restricted access - publisher's policy
    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ...