Exploració per autor "Tubella Murgadas, Jordi"
Ara es mostren els items 1-20 de 21
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A novel register renaming technique for out-of-order processors
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialModern superscalar processors support a large number of in-flight instructions, which requires sizeable register files. Conventional register renaming techniques allocate a new storage location, i.e. physical register, for ... -
A partial breadth-first execution model for prolog
(Institute of Electrical and Electronics Engineers (IEEE), 1994)
Text en actes de congrés
Accés obertMEM (Multipath Execution Model) is a novel model for the execution of Prolog programs which combines a depth-first and breadth-first exploration of the search tree. The breadth-first search allows more than one path of the ... -
An ultra low-power hardware accelerator for acoustic scoring in speech recognition
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialAccurate, real-time Automatic Speech Recognition (ASR) comes at a high energy cost, so accuracy has often to be sacrificed in order to fit the strict power constraints of mobile systems. However, accuracy is extremely ... -
Chrysso: an integrated power manager for constrained many-core processors
(Association for Computing Machinery (ACM), 2015)
Text en actes de congrés
Accés obertModern microprocessors are increasingly power-constrained as a result of slowed supply voltage scaling (end of Dennard scaling) in conjunction with the transistor density scaling (Moore's Law). Existing many-core power ... -
Compiler analysis for trace-level speculative multithreaded architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertTrace-level speculative multithreaded processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating ... -
Control speculation in multithreaded processors through dynamic loop detection
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertThis paper presents a mechanism to dynamically detect the loops that are executed in a program. This technique detects the beginning and the termination of the iterations and executions of the loops without compiler/user ... -
Exploiting path parallelism in logic programming
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertThis paper presents a novel parallel implementation of Prolog. The system is based on Multipath, a novel execution model for Prolog that implements a partial breadth-first search of the SLD-tree. The paper focusses on the ... -
Hardware/software mechanisms for protecting an IDS against algorithmic complexity attacks
(Institute of Electrical and Electronics Engineers (IEEE), 2012)
Text en actes de congrés
Accés restringit per política de l'editorialIntrusion Detection Systems (IDS) have emerged as one of the most promising ways to secure systems in the network. An IDS like the popular Snort[17] detects attacks on the network using a database of previous attacks. So ... -
Improving the performance efficiency of an IDS by exploiting temporal locality in network traffic
(2012)
Text en actes de congrés
Accés restringit per política de l'editorialNetwork traffic has traditionally exhibited temporal locality in the header field of packets. Such locality is intuitive and is a consequence of the semantics of network protocols. However, in contrast, the locality in the ... -
Improving the resilience of an IDS against performance throttling attacks
(Springer, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialIntrusion Detection Systems (IDS) have emerged as one of the most promising ways to secure systems in the network. To be effective against evasion attempts, the IDS must provide tight bounds on performance. Otherwise an ... -
La Influencia del orden de las preguntas en los exámenes de primer curso
(Universitat Jaume I. Escola Superior de Tecnologia i Ciències Experimentals, 2013-07-10)
Text en actes de congrés
Accés obertEl orden de las preguntas en un examen no debería tener influencia en sus resultados. Sin embargo, los autores tenemos la sensación de que los estudiantes de primero suelen ser secuenciales a la hora de resolver los ... -
Lightweight register file caching in collector units for GPUs
(Association for Computing Machinery (ACM), 2023)
Text en actes de congrés
Accés obertModern GPUs benefit from a sizable Register File (RF) to provide fine-grained thread switching. As the RF is huge and accessed frequently, it consumes a considerable share of the dynamic energy of the GPU. Designing a ... -
Multipath: un sistema para la programación lógica
(Universitat Politècnica de Catalunya, 1996-11-13)
Tesi
Accés obert -
Performance analysis and optimization of automatic speech recognition
(2018-10-01)
Article
Accés obertFast and accurate Automatic Speech Recognition (ASR) is emerging as a key application for mobile devices. Delivering ASR on such devices is challenging due to the compute-intensive nature of the problem and the power ... -
Shared resource aware scheduling on power-constrained tiled many-core processors
(2017-02-01)
Article
Accés obertPower management through dynamic core, cache and frequency adaptation is becoming a necessity in today’s power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation ... -
Shared resource aware scheduling on power-constrained tiled many-core processors
(Association for Computing Machinery (ACM), 2016)
Text en actes de congrés
Accés obertPower management through dynamic core, cache and frequency adaptation is becoming a necessity in today's power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation ... -
Thread partitioning and value prediction for exploiting speculative thread-level parallelism
(2004-02)
Article
Accés obertSpeculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model ... -
Trace-level reuse
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertTrace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, the instructions that make up such traces ... -
Trace-level speculative multithreaded architecture
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertThis paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectively. The architecture presents two main ... -
Una herramienta automática de feedback para ensamblador
(2008-10)
Report de recerca
Accés obertUn estudiante de primer curso de Ingeniería en Informática debe adquirir la capacidad de analizar y depurar códigos, tanto a alto nivel como en ensamblador. Este proceso requiere una participación activa por parte de los ...
