Ara es mostren els items 1-20 de 23

  • A Divide-and-Conquer Approach for Cell Routing using Litho-friendly Layouts 

    Vidal Obiols, Alexandre (Universitat Politècnica de Catalunya, 2013-06-17)
    Projecte/Treball Final de Carrera
    Accés restringit per acord de confidencialitat
  • Algorithmic and architectural techniques for the design of low-energy resilient applications 

    Moreno Vega, Alberto (Universitat Politècnica de Catalunya, 2013-06)
    Projecte/Treball Final de Carrera
    Accés restringit per acord de confidencialitat
  • Algorithms and methodologies for interconnect reliability analysis of integrated circuits 

    Jain, Palkesh (Universitat Politècnica de Catalunya, 2017-05-05)
    Tesi
    Accés obert
    The phenomenal progress of computing devices has been largely made possible by the sustained efforts of semiconductor industry in innovating techniques for extremely large-scale integration. Indeed, gigantically integrated ...
  • An environment for the automatic verification of digital circuits 

    San Pedro Martín, Javier de (Universitat Politècnica de Catalunya, 2011-05-17)
    Projecte/Treball Final de Carrera
    Accés obert
    English: The aim of this project is to implement a system for the automatic verification of digital circuits written in a high-level hardware description language (Verilog), to be potentially used to assist a electronic ...
  • A Simulation framework for hierarchical Network-on-Chip systems 

    San Pedro Martín, Javier de (Universitat Politècnica de Catalunya, 2012-06-22)
    Projecte Final de Màster Oficial
    Accés obert
    Today, even the simplest laptop processor has at least four cores and a graphics card containing tens of cores. It is not hard to find more performance- oriented processors with hundreds of cores, and it is expected to ...
  • Automatic synthesis and optimization of chip multiprocessors 

    Nikitin, Nikita (Universitat Politècnica de Catalunya, 2013-04-05)
    Tesi
    Accés obert
    The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental ...
  • Clustering for the optimisation of asynchronous controllers 

    Casanova Bachs, Jonàs (Universitat Politècnica de Catalunya, 2008-06-25)
    Projecte Final de Màster Oficial
    Accés obert
  • Design of an environment for solving pseudo-boolean optimization problems 

    Benedí, Marc (Universitat Politècnica de Catalunya, 2018-06-26)
    Treball Final de Grau
    Accés obert
    This dissertation addresses several approaches with the common goal of reducing the time required to solve Pseudo-Boolean minimisation problems. A C++ library has been developed which allows representing Pseudo-Boolean ...
  • Disseny i implementació d'un processador en un llenguatge de descripció de Hardware 

    Miralpeix Anglerill, Marta (Universitat Politècnica de Catalunya, 2011-03-01)
    Projecte/Treball Final de Carrera
    Accés obert
    Aquest propòsit és el fil conductor del projecte, del qual es deriven quatre objectius més concrets: Disseny del processador CAL16, sempre complint les característiques de modularitat i extensibilitat, fet que permetrà ...
  • Elastic Esterel 

    Galcerán Oms, Marc (Universitat Politècnica de Catalunya, 2007-06-25)
    Projecte Final de Màster Oficial
    Accés obert
    The aim of this master's thesis is to elasticize Esterel. Esterel is an imperative hardware description language (HDL) used to describe reactive systems, and oriented to specify control systems. It belongs to the family ...
  • Enhancing large format printer reliability using machine learning 

    Badia Sampera, Arnau (Universitat Politècnica de Catalunya, 2018-07-04)
    Treball Final de Grau
    Accés restringit per acord de confidencialitat
    Realitzat a/amb:  Hewlett-Packard Company
  • Library-free technology mapping for VLSI circuits with regular layouts 

    Alvarez Ruiz, Alex (Universitat Politècnica de Catalunya, 2014-07)
    Projecte Final de Màster Oficial
    Accés obert
    Technology mapping is the task to transform a technology independent logic network into a mapped network using gates from a library, optimizing some objective function such total area, delay or power consumption. As stated, ...
  • Loop pipelining with resource and timing constraints 

    Sánchez Carracedo, Fermín (Universitat Politècnica de Catalunya, 1996-01-12)
    Tesi
    Accés obert
    Developing efficient programs for many of the current parallel computers is not easy due to the architectural complexity of those machines. The wide variety of machine organizations often makes it more difficult to port ...
  • Machine learning techniques for resource prediction in nanoelectronic circuit design 

    Ricart Geli, Narcís (Universitat Politècnica de Catalunya, 2017-07-03)
    Projecte Final de Màster Oficial
    Accés obert
    This master’s thesis is about the use of machine learning techniques in the field of nanoelectronic circuit design. It has been developed in collaboration with eSilicon Corporation, which is a company specialized in ...
  • Multi-clustering net model for VLSI placement 

    Ziyatdinov, Andrey (Universitat Politècnica de Catalunya, 2008-09-07)
    Projecte Final de Màster Oficial
    Accés obert
  • Process mining using convex polytopes 

    Alemany Puig, Lluís (Universitat Politècnica de Catalunya, 2017-01-23)
    Treball Final de Grau
    Accés obert
    Process Mining is a relatively young field of study that highlights the difficulty to infer models of processes from which to extract enough information to make predictions about its behaviour, find bottlenecks and ...
  • Reducing energy with asynchronous circuits 

    Rivas Barragan, Daniel (Universitat Politècnica de Catalunya, 2012-06-27)
    Projecte/Treball Final de Carrera
    Accés obert
    Reducing energy consumption using asynchronous circuits. The elastic clocks approach has been implemented along with a closed-feedback loop in order to achieve a lower energy consumption along with more reliability in ...
  • Relative timing based verification of concurrent systems 

    Peña Basurto, Marco A. (Marco Antonio) (Universitat Politècnica de Catalunya, 2003-04-29)
    Tesi
    Accés obert
    La tesi presenta una nova teoria i una metodologia per a la verificació formal de propietats de seguretat en sistemes temporitzats. El correcte funcionament d'aquests sistemes no només depèn d'un conjunt de propietats ...
  • SAT-based algorithms for internal cell routing in nanoelectronic circuits 

    Vidal Obiols, Alexandre (Universitat Politècnica de Catalunya, 2015-10-15)
    Projecte Final de Màster Oficial
    Accés obert
    This thesis presents the extension of a routing framework for the internal routing of standard cells. We extend the original Boolean formulation and modify a SAT-solver to take advantage of the new variables. Our aim is ...
  • Structure discovery techniques for circuit design and process model visualization 

    San Pedro Martín, Javier de (Universitat Politècnica de Catalunya, 2017-10-27)
    Tesi
    Accés obert
    Graphs are one of the most used abstractions in many knowledge fields because of the easy and flexibility by which graphs can represent relationships between objects. The pervasiveness of graphs in many disciplines means ...