Exploració per autor "Cortadella, Jordi"
Ara es mostren els items 1-20 de 52
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A boolean rule-based approach for manufacturability-aware cell routing
(2014-03-01)
Article
Accés obertAn approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ... -
Adaptive clock with useful jitter
(2015-05-19)
Report de recerca
Accés obertThe growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ... -
A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects
(2016-06-01)
Article
Accés obertA new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and ... -
A hierarchical approach for generating regular floorplans
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertThe complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more ... -
A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertThe advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ... -
Architectural exploration of large-scale hierarchical chip multiprocessors
(2013)
Article
Accés restringit per política de l'editorialThe continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more ... -
Area-optimal transistor folding for 1-D gridded cell design
(2013-11)
Article
Accés obertThe 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which ... -
A Relational view of subgraph isomorphism
(1999-10)
Report de recerca
Accés obertThis paper presents a novel approach to the problem of finding all subgraph isomorphisms of a (pattern) graph into another (target) graph. A relational formulation of the problem, combined with a representation of relations ... -
A retargetable and accurate methodology for logic-IP-internal electromigration assessment
(2015)
Text en actes de congrés
Accés obertA new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification ... -
A Structural encoding technique for the synthesis of asynchronous circuits
(2000-12)
Report de recerca
Accés obertThis paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ... -
Asynchronous interface specification, analysis and synthesis
(1998-03)
Report de recerca
Accés obertInterfaces, by nature, are often asynchronous since they serve for connecting multiple distributed modules/agents without common clock. However, recent development in theory of asynchronous design in the area of ... -
Boolean decomposition for AIG optimization
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés obertRestructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the ... -
Discovering duplicate tasks in transition systems for the simplification of process models
(Springer, 2016)
Text en actes de congrés
Accés obertThis work presents a set of methods to improve the understandability of process models. Traditionally, simplification methods trade off quality metrics, such as fitness or precision. Conversely, the methods proposed in ... -
Divide-and-conquer strategies for process mining
(2009-03)
Report de recerca
Accés obertThe main goal of Process Mining is to extract process models from logs of a system. Among the possible models to represent a process, Petri nets is an ideal candidate due to its graphical representation, clear semantics ... -
Evaluating A+B=K conditions in constant time
(Institute of Electrical and Electronics Engineers (IEEE), 1988)
Text en actes de congrés
Accés obertThe authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, ... -
Evaluation of A+B=K conditions without carry propagation
(Institute of Electrical and Electronics Engineers (IEEE), 1992-11)
Article
Accés obertThe response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A+B=K is addressed. Although an addition is involved in the comparison, it is shown that ... -
Hardware primitives for the synthesis of multithreaded elastic systems
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Text en actes de congrés
Accés obertElastic systems operate in a dataflow-like mode using a distributed scalable control and tolerating variable-latency computations. At the same time, multithreading increases the utilization of processing units and hides ... -
High-radix division and square-root with speculation
(Institute of Electrical and Electronics Engineers (IEEE), 1994-08)
Article
Accés obertThe speed of high-radix digit-recurrence dividers and square-root units is mainly determined by the complexity of the result-digit selection. We present a scheme in which a simpler function speculates the result digit, ... -
Increasing the robustness of digital circuits with ring oscillator clocks
(2017)
Text en actes de congrés
Accés obertTechnology scaling enables lower supply voltages, but also increases power density of integrated circuits. In this context, power integrity becomes a major concern in the implementation of highperformance designs. This ... -
Jutge.org: characteristics and experiences
(2018-07)
Article
Accés obertJutge.org is an open educational online programming judge designed for students and instructors, featuring a repository of problems that is well organized by courses, topics and difficulty. Internally, Jutge.org uses a ...
