Browsing by Author "Cortadella, Jordi"
Now showing items 1-20 of 124
-
A boolean rule-based approach for manufacturability-aware cell routing
(2014-03-01)
Article
Open AccessAn approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ... -
A case study for the verification of complex timed circuits: IPCMOS
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Conference report
Open AccessThe verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ... -
Adaptive clock with useful jitter
(2015-05-19)
External research report
Open AccessThe growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ... -
A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects
(2016-06-01)
Article
Open AccessA new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and ... -
A hierarchical approach for generating regular floorplans
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Open AccessThe complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more ... -
A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Open AccessThe advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ... -
A mathematical formulation of the loop pipelining problem
(Universitat Politècnica de Catalunya (UPC), 1996)
Conference report
Open AccessThis paper presents a mathematical model for the loop pipelining problem that considers several parameters for optimization and supports any combination of resource and timing constraints. The unrolling degree of the loop ... -
An asynchronous architecture model for behavioral synthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1993)
Conference report
Open AccessAn asynchronous architecture model for behavioral synthesis is presented. The basis of the model lies in a distributed control structure consisting of multiple communicating processes. Data processing is performed by ... -
An efficient unique state coding algorithm for signal transition graphs
(Institute of Electrical and Electronics Engineers (IEEE), 1993)
Conference report
Open AccessCurrent algorithms to force the complete state coding (CSC) property for signal transition graphs work on the state graph and, therefore require exponential time and space. Polynomial algorithms have been only proposed for ... -
A new look at the conditions for the synthesis of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Conference report
Open AccessThis paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures ... -
A radix-16 SRT division unit with speculation of the quotient digits
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessThe speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approach that extends the theory developed for ... -
Architectural exploration of large-scale hierarchical chip multiprocessors
(2013)
Article
Restricted access - publisher's policyThe continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more ... -
Area-optimal transistor folding for 1-D gridded cell design
(2013-11)
Article
Open AccessThe 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which ... -
A recursive paradigm to solve boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 2009-04)
Article
Open AccessA Boolean relation can specify some types of flexibility of a combinational circuit that cannot be expressed with don't cares. Several problems in logic synthesis, such as Boolean decomposition or multilevel minimization, ... -
A region-based algorithm for discovering Petri nets from event logs
(Springer, 2008)
Conference report
Open AccessThe paper presents a new method for the synthesis of Petri nets from event logs in the area of Process Mining. The method derives a bounded Petri net that over-approximates the behavior of an event log. The most important ... -
A region-based theory for state assignment in speed-independent circuits
(1997-08)
Article
Open AccessState assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair ... -
A Relational view of subgraph isomorphism
(1999-10)
External research report
Open AccessThis paper presents a novel approach to the problem of finding all subgraph isomorphisms of a (pattern) graph into another (target) graph. A relational formulation of the problem, combined with a representation of relations ... -
A retargetable and accurate methodology for logic-IP-internal electromigration assessment
(2015)
Conference report
Open AccessA new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification ... -
A Structural encoding technique for the synthesis of asynchronous circuits
(2000-12)
External research report
Open AccessThis paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ... -
A symbolic algorithm for the synthesis of bounded Petri nets
(Springer, 2008)
Conference report
Open AccessThis paper presents an algorithm for the synthesis of bounded Petri nets from transition systems. A bounded Petri net is always provided in case it exists. Otherwise, the events are split into several transitions to guarantee ...
