Ara es mostren els items 1-20 de 81

  • A boolean rule-based approach for manufacturability-aware cell routing 

    Cortadella, Jordi; Petit Silvestre, Jordi; Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2014-03-01)
    Article
    Accés obert
    An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ...
  • Adaptive clock with useful jitter 

    Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (2015-05-19)
    Report de recerca
    Accés obert
    The growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ...
  • A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects 

    Jain, Palkesh; Cortadella, Jordi; Sapatnekar, Sachin S. (2016-06-01)
    Article
    Accés obert
    A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and ...
  • A hierarchical approach for generating regular floorplans 

    San Pedro Martín, Javier de; Cortadella, Jordi; Roca Pérez, Antoni (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Text en actes de congrés
    Accés obert
    The complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more ...
  • A hierarchical mathematical model for automatic pipelining and allocation using elastic systems 

    Cortadella, Jordi; Petit Silvestre, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Text en actes de congrés
    Accés obert
    The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ...
  • An asynchronous architecture model for behavioral synthesis 

    Cortadella, Jordi; Badia Sala, Rosa Maria (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Text en actes de congrés
    Accés obert
    An asynchronous architecture model for behavioral synthesis is presented. The basis of the model lies in a distributed control structure consisting of multiple communicating processes. Data processing is performed by ...
  • An efficient unique state coding algorithm for signal transition graphs 

    Pastor Llorens, Enric; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Text en actes de congrés
    Accés obert
    Current algorithms to force the complete state coding (CSC) property for signal transition graphs work on the state graph and, therefore require exponential time and space. Polynomial algorithms have been only proposed for ...
  • A new look at the conditions for the synthesis of speed-independent circuits 

    Pastor Llorens, Enric; Cortadella, Jordi; Roig Mansilla, Oriol (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Text en actes de congrés
    Accés obert
    This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures ...
  • Architectural exploration of large-scale hierarchical chip multiprocessors 

    Nikitin, Nikita; San Pedro Martín, Javier de; Cortadella, Jordi (2013)
    Article
    Accés restringit per política de l'editorial
    The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more ...
  • Area-optimal transistor folding for 1-D gridded cell design 

    Cortadella, Jordi (2013-11)
    Article
    Accés obert
    The 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which ...
  • A recursive paradigm to solve boolean relations 

    Baneres, David; Cortadella, Jordi; Kishinevsky, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2009-04)
    Article
    Accés obert
    A Boolean relation can specify some types of flexibility of a combinational circuit that cannot be expressed with don't cares. Several problems in logic synthesis, such as Boolean decomposition or multilevel minimization, ...
  • A region-based theory for state assignment in speed-independent circuits 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (1997-08)
    Article
    Accés obert
    State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair ...
  • A Relational view of subgraph isomorphism 

    Cortadella, Jordi; Valiente Feruglio, Gabriel Alejandro (1999-10)
    Report de recerca
    Accés obert
    This paper presents a novel approach to the problem of finding all subgraph isomorphisms of a (pattern) graph into another (target) graph. A relational formulation of the problem, combined with a representation of relations ...
  • A retargetable and accurate methodology for logic-IP-internal electromigration assessment 

    Jain, Palkesh; Sapatnekar, Sachin S.; Cortadella, Jordi (2015)
    Text en actes de congrés
    Accés obert
    A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification ...
  • A Structural encoding technique for the synthesis of asynchronous circuits 

    Carmona Vargas, Josep; Cortadella, Jordi; Pastor Llorens, Enric (2000-12)
    Report de recerca
    Accés obert
    This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ...
  • Asynchronous interface specification, analysis and synthesis 

    Kishinewsky, M; Cortadella, Jordi; Kondratyev, A; Lavagno, L (1998-03)
    Report de recerca
    Accés obert
    Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed modules/agents without common clock. However, recent development in theory of asynchronous design in the area of ...
  • Boolean decomposition for AIG optimization 

    Machado, Lucas; Cortadella, Jordi (Association for Computing Machinery (ACM), 2017)
    Text en actes de congrés
    Accés obert
    Restructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the ...
  • Checking signal transition graph implementability by symbolic bdd traversal 

    Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Pastor Llorens, Enric; Roig Mansilla, Oriol; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Text en actes de congrés
    Accés obert
    This paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification ...
  • Decomposition and technology mapping of speed-independent circuits using Boolean relations 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Pastor Llorens, Enric; Yakovlev, Alex (1999-09)
    Article
    Accés obert
    This paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available ...
  • Deriving Petri nets from finite transition systems 

    Cortadella, Jordi; Kishinevsky, Michael; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1998-08)
    Article
    Accés obert
    This paper presents a novel method to derive a Petri net from any specification model that can be mapped into a state-based representation with arcs labeled with symbols from an alphabet of events (a Transition System, ...