Browsing by Author "Cortadella Fortuny, Jordi"
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A boolean rule-based approach for manufacturability-aware cell routing
Cortadella Fortuny, Jordi; Petit Silvestre, Jordi; Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2014-03-01)
Article
Open AccessAn approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ... -
Adaptive clock with useful jitter
Cortadella Fortuny, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (2015-05-19)
External research report
Open AccessThe growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ... -
A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects
Jain, Palkesh; Cortadella Fortuny, Jordi; Sapatnekar, Sachin S. (2016-06-01)
Article
Open AccessA new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and ... -
A hierarchical approach for generating regular floorplans
San Pedro Martín, Javier de; Cortadella Fortuny, Jordi; Roca Pérez, Antoni (Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Open AccessThe complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more ... -
Architectural exploration of large-scale hierarchical chip multiprocessors
Nikitin, Nikita; San Pedro Martín, Javier de; Cortadella Fortuny, Jordi (2013)
Article
Restricted access - publisher's policyThe continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more ... -
Area-optimal transistor folding for 1-D gridded cell design
Cortadella Fortuny, Jordi (2013-11)
Article
Open AccessThe 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which ... -
A Relational view of subgraph isomorphism
Cortadella Fortuny, Jordi; Valiente Feruglio, Gabriel Alejandro (1999-10)
External research report
Open AccessThis paper presents a novel approach to the problem of finding all subgraph isomorphisms of a (pattern) graph into another (target) graph. A relational formulation of the problem, combined with a representation of relations ... -
A retargetable and accurate methodology for logic-IP-internal electromigration assessment
Jain, Palkesh; Sapatnekar, Sachin S.; Cortadella Fortuny, Jordi (2015)
Conference report
Open AccessA new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification ... -
A Structural encoding technique for the synthesis of asynchronous circuits
Carmona Vargas, Josep; Cortadella Fortuny, Jordi; Pastor Llorens, Enric (2000-12)
External research report
Open AccessThis paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ... -
Asynchronous interface specification, analysis and synthesis
Kishinewsky, M; Cortadella Fortuny, Jordi; Kondratyev, A; Lavagno, L (1998-03)
External research report
Open AccessInterfaces, by nature, are often asynchronous since they serve for connecting multiple distributed modules/agents without common clock. However, recent development in theory of asynchronous design in the area of ... -
Boolean decomposition for AIG optimization
Machado, Lucas; Cortadella Fortuny, Jordi (Association for Computing Machinery (ACM), 2017)
Conference report
Open AccessRestructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the ... -
Discovering duplicate tasks in transition systems for the simplification of process models
San Pedro Martín, Javier de; Cortadella Fortuny, Jordi (Springer, 2016)
Conference report
Open AccessThis work presents a set of methods to improve the understandability of process models. Traditionally, simplification methods trade off quality metrics, such as fitness or precision. Conversely, the methods proposed in ... -
Divide-and-conquer strategies for process mining
Carmona Vargas, Josep; Cortadella Fortuny, Jordi; Kishinevsky, Mike (2009-03)
External research report
Open AccessThe main goal of Process Mining is to extract process models from logs of a system. Among the possible models to represent a process, Petri nets is an ideal candidate due to its graphical representation, clear semantics ... -
Hardware primitives for the synthesis of multithreaded elastic systems
Dimitrakopoulos, George N.; Seitanidis, I.; Psarras, A.; Tsiouris, K.; Mattheakis, Pavlos M.; Cortadella Fortuny, Jordi (European Interactive Digital Advertising Alliance (EDAA), 2014)
Conference report
Open AccessElastic systems operate in a dataflow-like mode using a distributed scalable control and tolerating variable-latency computations. At the same time, multithreading increases the utilization of processing units and hides ... -
Increasing the robustness of digital circuits with ring oscillator clocks
Machado, Lucas; Roca Pérez, Antoni; Cortadella Fortuny, Jordi (2017)
Conference report
Open AccessTechnology scaling enables lower supply voltages, but also increases power density of integrated circuits. In this context, power integrity becomes a major concern in the implementation of highperformance designs. This ... -
Jutge.org: characteristics and experiences
Petit Silvestre, Jordi; Roura Ferret, Salvador; Carmona Vargas, Josep; Cortadella Fortuny, Jordi; Duch Brown, Amalia; Giménez, Omer; Mani, Anaga; Mas Rovira, Jan; Rodríguez Carbonell, Enric; Rubio Gimeno, Alberto; San Pedro Martín, Javier de; Venkataramani, Divya (2017-07-04)
Article
Open AccessJutge.org is an open educational online programming judge designed for students and instructors, featuring a repository of problems that is well organized by courses, topics and difficulty. Internally, Jutge.org uses a ... -
Keeping control transfer instructions out of the pipeline in architectures without condition codes
Cortadella Fortuny, Jordi; Llaberia Griñó, José M.; González Colás, Antonio María (1987-05)
External research report
Open AccessThe execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ... -
Log-based simplification of process models
San Pedro Martín, Javier de; Carmona Vargas, Josep; Cortadella Fortuny, Jordi (Springer, 2015)
Conference report
Open AccessThe visualization of models is essential for user-friendly human-machine interactions during Process Mining. A simple graphical representation contributes to give intuitive information about the behavior of a system. ... -
Logic decomposition of incompletely specified functions
Cortadella Fortuny, Jordi (2001-06)
External research report
Open AccessThe logic decomposition of incompletely specified functions (ISFs) is studied. A theoretical support based on ternary algebras is provided. This support aims at the logic decomposition of ISFs. A partial order is defined ... -
Measuring the tolerance of self-adaptive clocks to supply voltage noise
Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Cortadella Fortuny, Jordi (2011)
Conference report
Open AccessSimultaneous switching noise has become an important issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. ...