Now showing items 1-20 of 182

  • A case for acoustic wave detectors for soft-errors 

    Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (2016-01-01)
    Article
    Restricted access - publisher's policy
    The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena, making soft errors an important challenge in future microprocessors. New techniques ...
  • Accurate off-line phase classification for HW/SW co-designed processors 

    Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (Association for Computing Machinery (ACM), 2014)
    Conference report
    Open Access
    Evaluation techniques in microprocessor design are mostly based on simulating selected application's samples using a cycle-accurate simulator. These samples usually correspond to different phases of the application stream. ...
  • A co-designed HW/SW approach to general purpose program acceleration using a programmable functional unit 

    Deb, Abhishek; Codina Viñas, Josep M.; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Conference report
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    In this paper, we propose a novel programmable functional unit (PFU) to accelerate general purpose application execution on a modern out-of-order x86 processor in a complexity-effective way. Code is transformed and ...
  • A cost-effective clustered architecture 

    Canal Corretger, Ramon; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute ...
  • A detailed methodology to compute soft error rates in advanced technologies 

    Riera Villanueva, Marc; Canal Corretger, Ramon; Abella, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the ...
  • A Dynamically Adaptable Hardware Transactional Memory 

    Lupon Navazo, Marc; Magklis, Grigorios; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
    Conference report
    Open Access
    Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-place in memory and resolve conflicts ...
  • AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures 

    Aleta Ortega, Alexandre; Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María; Kaeli, D (2009-06)
    Article
    Open Access
    This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the ...
  • A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1998)
    Conference report
    Open Access
    The paper proposes an algorithm for computing symmetric eigenvalues and eigenvectors that uses a one-sided Jacobi approach and is targeted to a multicomputer in which nodes can be arranged as a two-dimensional mesh with ...
  • A methodology for user-oriented scalability analysis 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María; Marí, Carme (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Conference report
    Open Access
    Scalability analysis provides information about the effectiveness of increasing the number of resources of a parallel system. Several methods have been proposed which use different approaches to provide this information. ...
  • A methodology for user-oriented scalability analysis. 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María; Mari Vila, Carme (IEEE, 1997-07-14)
    Conference report
    Open Access
    Scalability analysis provides information about the effectiveness of increasing the number of resources of a parallel system. Several methods have been proposed which use different approaches to provide this information. ...
  • Analysis and optimization of engines for dynamically typed languages 

    Dot Artigas, Gem; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
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    Dynamically typed programming languages have become very popular in the recent years. These languages ease the task of the programmer but introduce significant overheads since assumptions about the types of variables have ...
  • Analysis of CPI variance for dynamic binary translators/optimizers modules 

    Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (IEEE, 2012)
    Conference report
    Restricted access - publisher's policy
    Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed ...
  • Analysis of non-uniform cache architecture policies for chip-multiprocessors using the Parsec Benchmark Suite 

    Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María (Association for Computing Machinery (ACM), 2009)
    Conference report
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    Non-Uniform Cache Architectures (NUCA) have been proposed as a solution to overcome wire delays that will dominate on-chip latencies in Chip Multiprocessor designs in the near future. This novel means of organization divides ...
  • Analyzing data locality in numeric applications 

    Sánchez Navarro, F. Jesús; González Colás, Antonio María (2000-07)
    Article
    Open Access
    In this article, we introduce SPLAT (Static and Profiled Data Locality Analysis Tool). The tool's purpose is to provide a fast study of memory behavior without the necessity of a costly memory simulator. SPLAT consists of ...
  • Anaphase: a fine-grain thread decomposition scheme for speculative multithreading 

    Madriles Gimeno, Carles; López Muñoz, Pedro; Codina Viñas, Josep M.; Gibert Codina, Enric; Latorre Salinas, Fernando; Martínez Vicente, Alejandro; Martinez, Raul; González Colás, Antonio María (IEEE Computer Society, 2009)
    Conference report
    Open Access
    Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not provide benefits when executing serial ...
  • An efficient solver for Cache Miss Equations 

    Bermudo, Nerina; Vera Rivera, Francisco Javier; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2000)
    Conference report
    Open Access
    Cache Miss Equations (CME) (S. Ghosh et al., 1997) is a method that accurately describes the cache behavior by means of polyhedra. Even though the computation cost of generating CME is a linear function of the number of ...
  • An energy-efficient memory unit for clustered microarchitectures 

    Bieschewski, Stefan; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2016-08-01)
    Article
    Open Access
    Whereas clustered microarchitectures themselves have been extensively studied, the memory units for these clustered microarchitectures have received relatively little attention. This article discusses some of the inherent ...
  • A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio (IEEE Computer Society Publications, 2012)
    Conference report
    Restricted access - publisher's policy
    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition ...
  • An ultra low-power hardware accelerator for acoustic scoring in speech recognition 

    Tabani, Hamid; Arnau Montañés, José María; Tubella Murgadas, Jordi; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference report
    Restricted access - publisher's policy
    Accurate, real-time Automatic Speech Recognition (ASR) comes at a high energy cost, so accuracy has often to be sacrificed in order to fit the strict power constraints of mobile systems. However, accuracy is extremely ...
  • An ultra low-power hardware accelerator for automatic speech recognition 

    Yazdani Aminabadi, Reza; Segura Salvador, Albert; Arnau Montañés, José María; González Colás, Antonio María (IEEE Press, 2016)
    Conference report
    Open Access
    Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost which is not affordable for the tiny power budget of mobile devices. ...