• Adaptive clock with useful jitter 

    Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (2015-05-19)
    Report de recerca
    Accés obert
    The growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ...
  • Algorithmic and architectural techniques for the design of low-energy resilient applications 

    Moreno Vega, Alberto (Universitat Politècnica de Catalunya, 2013-06)
    Projecte/Treball Final de Carrera
    Accés restringit per acord de confidencialitat
  • Reactive clocks with variability-tracking jitter 

    Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
    Accés obert
    The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits ...
  • Ring oscillator clocks and margins 

    Cortadella, Jordi; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés obert
    How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA ...
  • Synthesis of all-digital delay lines 

    Moreno Vega, Alberto; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    The synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure of merit of a DL is the fidelity to track variability. Unfortunately, ...
  • Synthesis of timing paths with delays adaptable to integrated circuit variability 

    Moreno Vega, Alberto (Universitat Politècnica de Catalunya, 2015-07-10)
    Projecte Final de Màster Oficial
    Accés obert
    This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce ...
  • Waveform Transition Graphs: a designer-friendly formalism for asynchronous behaviours 

    Cortadella, Jordi; Moreno Vega, Alberto; Sokolov, Danil; Yakovlev, Alex; Lloyd, David (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Comunicació de congrés
    Accés obert
    The paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the ...