Now showing items 1-9 of 9

  • Adaptive clock with useful jitter 

    Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (2015-05-19)
    External research report
    Open Access
    The growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ...
  • Algorithmic and architectural techniques for the design of low-energy resilient applications 

    Moreno Vega, Alberto (Universitat Politècnica de Catalunya, 2013-06)
    Master thesis (pre-Bologna period)
    Restricted access - confidentiality agreement
  • Reactive clocks with variability-tracking jitter 

    Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Open Access
    The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits ...
  • Ring oscillator clocks and margins 

    Cortadella, Jordi; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA ...
  • State encoding of asynchronous controllers using pseudo-boolean optimization 

    Moreno Vega, Alberto; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    State encoding of asynchronous controllers is a challenging problem that faces a vast space of solutions. Subtle differences in the insertion of signals may result in significant variations in the complexity of the logic. ...
  • Synthesis of all-digital delay lines 

    Moreno Vega, Alberto; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference report
    Open Access
    The synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure of merit of a DL is the fidelity to track variability. Unfortunately, ...
  • Synthesis of timing paths with delays adaptable to integrated circuit variability 

    Moreno Vega, Alberto (Universitat Politècnica de Catalunya, 2015-07-10)
    Master thesis
    Open Access
    This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce ...
  • Synthesis of variability-tolerant circuits with adaptive clocking 

    Moreno Vega, Alberto (Universitat Politècnica de Catalunya, 2019-03-08)
    Doctoral thesis
    Open Access
    Improvements in circuit manufacturing have allowed, along the years, increasingly complex designs. This has been enabled by the miniaturization that circuit components have undergone. But, in recent years, ...
  • Waveform Transition Graphs: a designer-friendly formalism for asynchronous behaviours 

    Cortadella, Jordi; Moreno Vega, Alberto; Sokolov, Danil; Yakovlev, Alex; Lloyd, David (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference lecture
    Open Access
    The paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the ...