Exploració per autor "Moreno Vega, Alberto"
Ara es mostren els items 1-9 de 9
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Adaptive clock with useful jitter
(2015-05-19)
Report de recerca
Accés obertThe growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ... -
Algorithmic and architectural techniques for the design of low-energy resilient applications
(Universitat Politècnica de Catalunya, 2013-06)
Projecte/Treball Final de Carrera
Accés restringit per acord de confidencialitat -
Reactive clocks with variability-tracking jitter
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertThe growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits ... -
Ring oscillator clocks and margins
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertHow much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA ... -
State encoding of asynchronous controllers using pseudo-boolean optimization
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertState encoding of asynchronous controllers is a challenging problem that faces a vast space of solutions. Subtle differences in the insertion of signals may result in significant variations in the complexity of the logic. ... -
Synthesis of all-digital delay lines
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertThe synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure of merit of a DL is the fidelity to track variability. Unfortunately, ... -
Synthesis of timing paths with delays adaptable to integrated circuit variability
(Universitat Politècnica de Catalunya, 2015-07-10)
Projecte Final de Màster Oficial
Accés obertThis project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce ... -
Synthesis of variability-tolerant circuits with adaptive clocking
(Universitat Politècnica de Catalunya, 2019-03-08)
Tesi
Accés obertImprovements in circuit manufacturing have allowed, along the years, increasingly complex designs. This has been enabled by the miniaturization that circuit components have undergone. But, in recent years, ... -
Waveform Transition Graphs: a designer-friendly formalism for asynchronous behaviours
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Comunicació de congrés
Accés obertThe paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the ...
