Exploració per autor "Radojković, Petar"
Ara es mostren els items 1-20 de 32
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Another trip to the wall: how much will stacked DRAM benefit HPC?
(Association for Computing Machinery (ACM), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialFirst defined two decades ago, the memory wall remains a fundamental limitation to system performance. Recent innovations in 3D-stacking technology enable DRAM devices with much higher bandwidths than traditional DIMMs. ... -
Characterizing the resource-sharing levels of the UltraSparc T2 processor
(Association for Computing Machinery (ACM), 2009)
Text en actes de congrés
Accés restringit per política de l'editorialThread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ... -
Cost-aware prediction of uncorrected DRAM errors in the field
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThis paper presents and evaluates a method to predict DRAM uncorrected errors, a leading cause of hardware failures in large-scale HPC clusters. The method uses a random forest classifier, which was trained and evaluated ... -
Cost-aware prediction of uncorrected DRAM errors in the field
(Barcelona Supercomputing Center, 2021-05)
Text en actes de congrés
Accés obertOne of the main causes of hardware failure in large-scale clusters is an uncorrected error in main memory [1]–[4]. Node failures are especially problematic in high-performance computing (HPC), where a single tightly-coupled ... -
Detailed tuning and validation of hardware simulators through microbenchmarks
(Barcelona Supercomputing Center, 2018-04-24)
Text en actes de congrés
Accés obert -
DRAM errors in the field: a statistical approach
(Association for Computing Machinery (ACM), 2019)
Text en actes de congrés
Accés obertThis paper summarizes our two-year study of corrected and uncor-rected errors on the MareNostrum 3 supercomputer, covering 2000 billion MB-hours of DRAM in the field. The study analyzes 4.5 million corrected and 71 uncorrected ... -
Enabling a reliable STT-MRAM main memory simulation
(Association for Computing Machinery, 2017-10)
Comunicació de congrés
Accés obertSTT-MRAM is a promising new memory technology with very desirable set of properties such as non-volatility, byte-addressability and high endurance. It has the potential to become the universal memory that could be incorporated ... -
Enabling a reliable STT-MRAM main memory simulation
(Barcelona Supercomputing Center, 2018-04-24)
Text en actes de congrés
Accés obert -
Energy efficient HPC on embedded SoCs : optimization techniques for mali GPU
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialA lot of effort from academia and industry has been invested in exploring the suitability of low-power embedded technologies for HPC. Although state-of-the-art embedded systems-on-chip (SoCs) inherently contain GPUs that ... -
HPC benchmarking: scaling right and looking beyond the average
(Springer, 2018)
Text en actes de congrés
Accés obertDesigning a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads that quantifies the ... -
Improving the effective use of multithreaded architectures : implications on compilation, thread assignment, and timing analysis
(Universitat Politècnica de Catalunya, 2013-07-19)
Tesi
Accés obertThis thesis presents cross-domain approaches that improve the effective use of multithreaded architectures. The contributions of the thesis can be classified in three groups. First, we propose several methods for thread ... -
Large-memory nodes for energy efficient high-performance computing
(Association for Computing Machinery (ACM), 2016)
Text en actes de congrés
Accés obertEnergy consumption is by far the most important contributor to HPC cluster operational costs, and it accounts for a significant share of the total cost of ownership. Advanced energy-saving techniques in HPC components have ... -
Main memory in HPC: do we need more or could we live with less?
(Barcelona Supercomputing Center, 2017-05-04)
Text en actes de congrés
Accés obertThis study analyzes the memory capacity requirements of important HPC benchmarks and applications. We find that the High Performance Conjugate Gradients benchmark could be an important success story for 3D-stacked memories ... -
Main memory in HPC: do we need more, or could we live with less?
(2017-03)
Article
Accés obertAn important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with ... -
Main memory latency simulation: the missing link
(Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés obertThe community accepted the need for a detailed simulation of main memory. Currently, the CPU simulators are usually coupled with the cycle-accurate main memory simulators. However, coupling CPU and memory simulators is not ... -
Mainstream vs. emerging HPC: metrics, trade-offs and lessons learned
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertVarious servers with different characteristics and architectures are hitting the market, and their evaluation and comparison in terms of HPC features is complex and multidimensional. In this paper, we share our experience ... -
Measuring operating system overhead on CMT processors
(IEEE Computer Society Publications, 2008)
Text en actes de congrés
Accés obertNumerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ... -
Measuring operating system overhead on Sun UltraSparc T1 processor
(2009-06)
Text en actes de congrés
Accés obertNumerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ... -
Microbenchmarks for detailed validation and tuning of hardware simulators
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialHardware simulators are indispensable tools for the computer architecture research. They are used by the academia and industry to prototype, explore and evaluate novel microarchitectural features. -
Overhead of the spin-lock loop in UltraSPARC T2
(2008-06-04)
Text en actes de congrés
Accés obertSpin locks are task synchronization mechanism used to provide mutual exclusion to shared software resources. Spin locks have a good performance in several situations over other synchronization mechanisms, i.e., when on ...
